AT21CS01 datasheet(22/47 Pages) MICROCHIP

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Write Operations

All write operations for the AT21CS01/11 begin with the master sending a Start condition, followed by a

device address byte (opcode Ah for the EEPROM and opcode Bh for the Security register) with the R/W

bit set to ‘0’ followed by the memory address byte. Next, the data value(s) to be written to the device are

sent. Data values must be sent in 8-bit increments to the device followed by a Stop condition. If a Stop

condition is sent somewhere other than at the byte boundary, the current write operation will be aborted.

The AT21CS01/11 allows single byte writes, partial page writes, and full page writes.

6.1

Device Behavior During Internal Write Cycle

To ensure that the address and data sent to the device for writing are not corrupted while any type of

internal write operation is in progress, commands sent to the device are blocked from being recognized

until the internal operation is completed. If a write interruption occurs (SI/O pulsed low) and is small

enough to not deplete the internal power storage, the device will NACK signaling that the operation is in

progress. If an interruption is longer than tDSCHG then internal write operation will be terminated and may

result in data corruption.

6.2

Byte Write

The AT21CS01/11 supports writing of a single 8-bit byte and requires a 7-bit memory word address to

select which byte to write.

Upon receipt of the proper device address byte (with opcode of Ah) and memory address byte, the

EEPROM will send a logic ‘0’ to signify an ACK. The device will then be ready to receive the data byte.

Following receipt of the complete 8-bit data byte, the EEPROM will respond with an ACK. A Stop

condition must then occur; however, since a Stop condition is defined as a null bit frame with SI/O pulled

high, the master does not need to drive the SI/O line to accomplish this. If a Stop condition is sent at any

other time, the write operation is aborted. After the Stop condition is complete, the EEPROM will enter an

internally self-timed write cycle, which will complete within a time of tWR, while the data is being

programmed into the nonvolatile EEPROM. The SI/O pin must be pulled high via the external pull-up

resistor during the entire tWR cycle. After the maximum tWR time has elapsed, the master may begin a

new bus transaction.

Note:

Any attempt to interrupt the internal write cycle by driving the SI/O line low may cause the byte

being programmed to be corrupted. Other memory locations within the memory array will not be

affected. Note Device Behavior During Internal Write Cycle for the behavior of the device while the

write cycle is in progress. If the master must interrupt a write operation, the SI/O line must be driven

low for tDSCHG as noted in Interrupting the Device during an Active Operation.

Figure 6-1. Byte Write

SI/O

MSB

ACK

by Slave

0 A2 A1 A0 0

Device Address

MSB

x A6 A5 A4 A3 A2 A1 A0

Memory Address

MSB

Data In Byte

ACK

by Slave

`ACK

by Slave

Stop Condition

by Master

Start Condition

by Master

Note:

x = Don’t Care bit in the place of A7 as this bit falls outside the 1-Kbit addressable range.

AT21CS01/AT21CS11

Datasheet

DS20005857A-page 22

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