AT21CS01 datasheet(13/47 Pages) MICROCHIP

13 / 47 page

However, if the device is busy, the master must drive SI/O for a longer time of tDSCHG to ensure the device

is reset as discussed in Interrupting the Device during an Active Operation. The Reset time forces any

internal charge storage within the device to be consumed, causing the device to lose all remaining

standby power available internally.

Upon SI/O being released for a sufficient amount of time to allow the device time to power-up and

initialize, the master must then always request a Discovery Response Acknowledge from the

AT21CS01/11 prior to any commands being sent to the device. The master can then determine if an

AT21CS01/11 is present by sampling for the Discovery Response Acknowledge from the device.

3.1.1.2

Device Response Upon Reset or Power-Up

After the device has been powered up or after the master has reset the device by holding the SI/O line

low for tRESET or tDSCHG, the master must then release the line which will be pulled high by an external

pull-up resistor. The master must then wait an additional minimum time of tRRT before the master can

request a Discovery Response Acknowledge from the device.

The Discovery Response Acknowledge sequence begins by the master driving the SI/O line low which

will start the AT21CS01/11 internal timing circuits. The master must continue to drive the line low for tDRR.

During the tDRR time, the AT21CS01/11 will respond by concurrently driving SI/O low. The device will

continue to drive SI/O low for a total time of tDACK. The master should sample the state of the SI/O line at

tMSDR past the initiation of tDRR. By definition, the tDACK minimum is longer than the tMSDR maximum time,

thereby ensuring the master can always correctly sample the SI/O for a level less than VIL. After the tDACK

time has elapsed, the AT21CS01/11 will release SI/O which will then be pulled high by the external

pull

‑up resistor.

The master must then wait tHTSS to create a Start condition before continuing with the first command (see

Start/Stop Condition for more details about Start conditions). By default, the device will come out of Reset

in High-Speed mode. Changing the device to Standard Speed mode is covered in Standard Speed Mode

(Opcode Dh). The AT21CS01/11 will power-up with its internal Address Pointer set to zero.

The timing requirements for the Reset and Discovery Response sequence for both Standard Speed and

High-Speed mode can be found in AT21CS01/11 AC Characteristics.

3.1.2

Interrupting the Device during an Active Operation

To conserve the stored energy within the onboard parasitic power system and minimize overall active

current, the AT21CS01/11 will not monitor the SI/O line for new commands while it is busy executing a

previously sent command. As a result, the device is not able to sense how long SI/O has been in a given

state. If the master requires to interrupt the device during an active operation, it must drive SI/O low long

enough to deplete all of its remaining stored power. This time is defined as tDSCHG, after which a normal

Discovery Response can begin by releasing the SI/O line.

Figure 3-1. Reset and Discovery Response Waveform

SI/O

tRESET / tDSCHG

VIL

VIH

MASTER

PULL-UP RESISTOR

AT21CS01

Begin Next

Command with

Start Condition

tRRT

tDACK

tMSDR

Master

Sampling

Window

tDRR

tPUP

tHTSS

AT21CS01/AT21CS11

Datasheet

DS20005857A-page 13

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