AT21CS01 datasheet(29/47 Pages) MICROCHIP

29 / 47 page

Figure 7-4. Sequential Read from a Random Read

SI/O

MSB

ACK

by Slave

0 A2 A1 A0 0

Device Address

MSB

x A6 A5 A4 A3 A2 A1 A0

Memory Address

MSB

Data Out Byte (n)

ACK

by Slave

ACK

by Master

Stop Condition

by Master

Start Condition

by Master

MSB

ACK

by Slave

0 A2 A1 A0 1

Device Address

Restart

by Master

MSB

Data Out Byte (n + x)

Dummy Write

NACK

by Master

7.4

Read Operations in the Security Register

The Security register can be read by using either a random read or a sequential read operation. Due to

the fact that the EEPROM and Security register share a single Address Pointer register, a “dummy write”

must be performed to correctly set the Address Pointer in the Security register. This is why a random read

or sequential read must be used as these sequences include a “dummy write.” Bits A7 through A5 are

"don’t care" bits as these fall outside the addressable range of the Security register. Current address

reads of the Security register are not supported.

In order to read the Security register, the device address byte must be specified with the opcode 1011b

(Bh) instead of the opcode 1010b (Ah).The Security register can be read to read the 64-bit serial number

or the remaining user-programmable data.

7.4.1

Serial Number Read

The lower eight bytes of the Security register contain a factory-programmed, unique, 64

‑bit serial number.

In order to ensure a unique value, the entire 64-bit serial number must be read starting at Security

read operation be used, ensuring that the random read sequence uses a device address byte with

opcode 1011b (Bh) specified in addition to the memory address byte being set to 00h.

The first byte read out of the 64-bit serial number is the product identifier (A0h). Following the product

identifier, a 48-bit unique number is contained in bytes 1 through 6. The last byte of the serial number

contains a cyclic redundancy check (CRC) of the other 56 bits. The CRC is generated using the

polynomial X8 + X5 + X4 + 1. The structure of the 64-bit serial number is depicted in Table 7-1.

Table 7-1. 64-Bit Factory-Programmed Serial Number Organization

Byte 0

Byte 1

Byte 2

Byte 3

Byte 4

Byte 5

Byte 6

Byte 7

8-bit

Product

Identifier

(A0h)

48-bit Unique Number

8-bit CRC

Value

After all eight bytes of the serial number have been read, the master can return a NACK (logic ‘1’)

response to end the read operation and return the device to the Standby mode. If the master sends an

ACK (logic ‘0’) instead of a NACK, then the next byte (address location 08h) in the Security register will

be output. If the end of the Security register is reached, then the Address Pointer will “roll over” back to

the beginning (address location 00h) of the Security register.

AT21CS01/AT21CS11

Datasheet

DS20005857A-page 29

AT21CS01 数据表(PDF) 29 Page - Microchip Technology

AT21CS01 数据表(HTML) 29 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

数据表下载

链接网址

AT21CS01 数据表(PDF) 29 Page - Microchip Technology

AT21CS01 数据表(HTML) 29 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

数据表 下载

链接网址

数据表下载