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FS32K148UFT0VLHT 数据表(PDF) 81 Page - NXP Semiconductors

部件名 FS32K148UFT0VLHT
功能描述  Voltage range: 2.7 V to 5.5 V Low-power Arm Cortex-M4F/M0 core with excellent energy efficiency
PDF  100 Pages
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制造商  NXP [NXP Semiconductors]
网页  http://www.nxp.com
标志 NXP - NXP Semiconductors

FS32K148UFT0VLHT 数据表(HTML) 81 Page - NXP Semiconductors

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Table 54. JTAG electrical specifications
Symb
ol
Description
Run Mode
HSRUN Mode
VLPR Mode (S32K1xx)
VLPR Mode (S32K14xW)
Unit
5.0 V IO
3.3 V IO
5.0 V IO
3.3 V IO
5.0 V IO
3.3 V IO
5.0 V IO
5.0 V IO
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min
Max
Min
Max
JI
TCLK frequency of operation
MHz
Boundary Scan
-
20
-
20
-
20
-
20
-
10
-
10
-
1
-
1
JTAG
-
20
-
20
-
20
-
20
-
10
-
10
-
1
-
1
J2
TCLK cycle period
1/JI
-
1/JI
-
1/JI
-
1/JI
-
1/JI
-
1/JI
-
1/J1
-
1/J1
-
ns
J3
TCLK clock pulse width
ns
Boundary Scan
JTAG
J4
TCLK rise and fall
times
-
1
-
1
-
1
-
1
-
1
-
1
-
1
-
1
ns
J5
Boundary scan input
data setup time to
TCLK rise
5
-
5
-
5
-
5
-
15
-
15
-
23
-
23
-
ns
J6
Boundary scan input
data hold time after
TCLK rise
5
-
5
-
5
-
5
-
8
-
8
-
20
-
20
-
ns
J7
TCLK low to boundary
scan output data valid
-
28
-
32
-
28
-
32
-
80
-
80
-
184
-
184
ns
J8
TCLK low to boundary
scan output data invalid
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
J9
TCLK low to boundary
scan output high-Z
-
28
-
32
-
28
-
32
-
80
-
80
-
184
-
184
ns
J10
TMS, TDI input data
setup time to TCLK rise
3
-
3
-
3
-
3
-
15
-
15
-
23
-
23
-
ns
J11
TMS, TDI input data
hold time after TCLK
rise
2
-
2
-
2
-
2
-
8
-
8
-
20
-
20
-
ns
J12
TCLK low to TDO data
valid
-
28
-
32
-
28
-
32
-
80
-
80
-
184
-
184
ns
J13
TCLK low to TDO data
invalid
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
ns
Table continues on the next page...



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