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WM8742GEDS/V 数据表(PDF) 11 Page - Cirrus Logic

部件名 WM8742GEDS/V
功能描述  24-bit 192 kHz DAC with Advanced Digital Filtering
PDF  66 Pages
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制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

WM8742GEDS/V 数据表(HTML) 11 Page - Cirrus Logic

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WM8742
Rev 4.4
11
TEST CONDITIONS
AVDD = 5V, DVDD = 3.3V, AGND, DGND = 0V, TA = +25
oC, 1kHz test signal, fs = 48kHz, MCLK = 512fs unless otherwise
stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Internal Analogue Filter
Bandwidth
-3dB
474
kHz
Passband edge response
20kHz
-0.0077
dB
Analogue Output Levels
PCM full scale differential
output level
Into 10k
Ω load, 0dBFS input
2
VRMS
DSD Direct differential
output level
Into 10k
Ω load, 0dB
DSD input
0.948
VRMS
DSD Plus differential output
level
Into 10k
Ω load, 0dB
DSD input
0.991
VRMS
Minimum resistance load
To midrail or AC coupled
2
k
Ω
Maximum capacitance load
1
nF
Output DC level
AVDD/2
V
Reference Levels
Potential divider resistance
AVDD to VMIDL/VMIDR and
VMIDL/VMIDR to AGND
10
k
Ω
Voltage at VMIDL/VMIDR
AVDD/2
V
Notes:
1.
Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, me
asured ‘A’ weighted
over a 20Hz to 20kHz bandwidth.
2.
All performance measurements done with 20kHz low pass filter. Failure to use such a filter will result in higher THD and lower
SNR and Dynamic Range readings than are found in the Electrical Characteristics. The low pass filter removes out of band
noise; although it is not audible it may affect dynamic specification values.
MASTER CLOCK TIMING
MCLK
t
MCLKL
t
MCLKH
t
MCLKY
V
IH
V
IL
Figure 1 Master Clock Timing Requirements
Test Conditions
AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25
oC
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Master Clock Timing Information
MCLK Master clock pulse width high
tMCLKH
10
ns
MCLK Master clock pulse width low
tMCLKL
10
ns
MCLK Master clock cycle time
tMCLKY
27
ns
MCLK Duty cycle
40:60
60:40
Table 1 MCLK Timing Requirements



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