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WM8742GEDS/V 数据表(PDF) 23 Page - Cirrus Logic |
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WM8742GEDS/V 数据表(HTML) 23 Page - Cirrus Logic |
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23 / 66 page ![]() WM8742 Rev 4.4 23 RIGHT JUSTIFIED MODE In right justified mode, the LSB is sampled on the rising edge of BCLK preceding a LRCLK transition. LRCLK is high during the left data word and low during the right data word. LEFT CHANNEL RIGHT CHANNEL 1/fs n 3 2 1 n-2 n-1 LSB MSB n 3 2 1 n-2 n-1 LSB MSB LRCLK BCLK DIN Figure 15 Right Justified Mode Timing Diagram I2S MODE In I2S mode, the MSB is sampled on the second rising edge of BCLK following a LRCLK transition. LRCLK is low during the left data word and high during the right data word. LEFT CHANNEL RIGHT CHANNEL LRCLK BCLK DIN 1/fs n 3 2 1 n-2 n-1 LSB MSB n 3 2 1 n-2 n-1 LSB MSB 1 BCLK 1 BCLK Figure 16 I2S Mode Timing Diagram |
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