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WM8742GEDS/V 数据表(PDF) 24 Page - Cirrus Logic |
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WM8742GEDS/V 数据表(HTML) 24 Page - Cirrus Logic |
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24 / 66 page ![]() WM8742 24 Rev 4.4 DSP MODE A In DSP mode A, the first bit is sampled on the BCLK rising edge following the one that detects a low to high transition on LRCLK. No BCLK edges are allowed between the data words. The word order is DIN left, DIN right. LRCLK BCLK DIN Input Word Length (IWL) 1/fs LEFT CHANNEL n 2 1 n-1 LSB MSB n 2 1 n-1 RIGHT CHANNEL NO VALID DATA 1 BCLK 1 BCLK Figure 17 DSP Mode A Timing Diagram DSP MODE B In DSP mode B, the first bit is sampled on the BCLK rising edge, which detects a low to high transition on LRCLK. No BCLK edges are allowed between the data words. The word order is DIN left, DIN right. LRCLK BCLK DIN Input Word Length (IWL) 1/fs LEFT CHANNEL n 2 1 n-1 LSB MSB n 2 1 n-1 RIGHT CHANNEL NO VALID DATA 1 Figure 18 DSP Mode B Timing Diagram |
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