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WM8742GEDS/V 数据表(PDF) 25 Page - Cirrus Logic |
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WM8742GEDS/V 数据表(HTML) 25 Page - Cirrus Logic |
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25 / 66 page ![]() WM8742 Rev 4.4 25 PCM MODE SAMPLING RATES The WM8742 supports master clock rates of 128fs to 768fs, where fs is the audio sampling frequency (LRCLK), typically 32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz, 176.4kHz or 192kHz. The WM8742 has a master clock detection circuit that automatically determines the relationship between the master clock frequency and the sampling rate. The master clock should be synchronised with LRCLK, although the WM8742 is tolerant of phase differences or jitter on this clock. SAMPLING RATE (LRCLK) MASTER CLOCK (MCLK) FREQUENCY (MHZ) 128fs 192fs 256fs 384fs 512fs 768fs 32kHz Unavailable Unavailable 8.192 12.288 16.384 24.576 44.1kHz Unavailable Unavailable 11.2896 16.9344 22.5792 33.8688 48kHz Unavailable Unavailable 12.288 18.432 24.576 36.864 88.2kHz 11.2896 16.9344 22.5792 33.8688 Unavailable Unavailable 96kHz 12.288 18.432 24.576 36.864 Unavailable Unavailable 176.4kHz 22.5792 33.8688 Unavailable Unavailable Unavailable Unavailable 192kHz 24.576 36.864 Unavailable Unavailable Unavailable Unavailable Table 11 Typical Relationships Between Master Clock Frequency and Sampling Rate in normal PCM mode 8FS MODE Operation in 8FS mode requires that audio data for left and right channels is input separately on two pins. DINR (pin 4) is the input for right channel data and DINL (pin 2) is the input for left channel data. Hardware control of the device is not available. The data can be input in two formats (left or right justified), selectable by register FMT[1:0], and two word lengths (20 or 24 bit), selectable by register IWL[1:0]. In both modes the data is clocked into the WM8742 MSB first. For left justified data the word start is identified by the falling edge of LRCLK. The data is clocked in on the next 20/24 BCLK rising edges. This format is compatible with industry-standard DSPs and decoders such as the PMD100. Sample 1 Sample 2 LRCLK BCLK DINL 1/8fs 1/8fs LSB MSB n 3 2 1 n-2 n-1 LSB MSB n 3 2 1 n-2 n-1 DINR LSB MSB n 3 2 1 n-2 n-1 LSB MSB n 3 2 1 n-2 n-1 Figure 19 8FS Mode Left Justified Timing Requirements For right justified mode, the data is justified to the rising edge of LRCLK and the data is clocked in on the preceding 20/24 BCLK rising edges before the LRCLK rising edge. This format is compatible with industry standard DSPs and decoders such as the DF1704 or SM5842. |
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