IS25LP032D-RKLA3:P datasheet(92/118 Pages) ISSI

92 / 118 page

IS25LP032D

IS25WP032D

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A12

08/04/2020

FAST READ QUAD IO DTR MODE OPERATION IN QPI MODE (FRQDTR, EDh)

The FRQDTR instruction in QPI mode utilizes all four IO lines to input the instruction code so that only two clocks

are required, while the FRQDTR instruction requires that the byte-long instruction code is shifted into the device

only via IO0 line in eight clocks. As a result, 6 command cycles will be reduced by the FRQDTR instruction in QPI

mode. In addition, subsequent address and data out are shifted in/out via all four IO lines like the FRQDTR

instruction. In fact, except for the command cycle, the FRQDTR operation in QPI mode is exactly same as the

FRQDTR operation in SPI mode.

It is not required to set QE bit

to “1”.before Fast Read Quad I/O DTR instruction in QPI mode.

The sequence of issuing FRQDTR instruction in QPI mode is: CE# goes low  Sending FRQDTR instruction (4-

bit per clock)  24-bit address interleave on IO3, IO2, IO1 & IO0 (8-bit per clock)  6 dummy clocks (configurable,

default is 6 clocks)  Data out interleave on IO3, IO2, IO1 & IO0 (8-bit per clock)  End FRQDTR operation by

driving CE# high at any time during data out.

If AXh (

where X is don’t care) is input for the mode bits during dummy cycles, the device will enter AX read operation

mode which enables subsequent FRQDTR execution skips command code. When the code is different from AXh,

the device exits the AX read operation. After finishing the read operation, device becomes ready to receive a new

command.

If the FRQDTR instruction in QPI mode is issued while a Program/Erase/Write Status Register cycle is in progress

(WIP=1), the instruction will be rejected without any effect on the current cycle.

Figure 8.69 FRQDTR Sequence In QPI Mode (with command decode cycles)

Instruction

= EDh

CE #

SCK

3-byte Address

Mode 3

Mode 0

20 16 12

5 1

21 17 13

4 0

IO0

IO1

22 18 14

23 19 15

8 4

9 5

10 6

11 7

6 Dummy Cycles

IO2

IO3

6 2

7 3

5 1

4 0

6 2

7 3

Data

Out

Data

Out

5 1

4 0

6 2

7 3

Mode Bits

...

Notes:

1. If the mode bits=AXh (

where X is don’t care), it can execute the AX read mode (without command). When the mode

bits are different from AXh, the device exits the AX read operation.

2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.11 Read Dummy Cycles.

3. Sufficient dummy cycles are required to avoid I/O contention. If the number of dummy cycles and AX bit cycles are

same, then X should be Hi-Z.

IS25LP032D-RKLA3:P 数据表(PDF) 92 Page - Integrated Silicon Solution, Inc

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