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IS25LP032D-RKLA3:P 数据表(PDF) 31 Page - Integrated Silicon Solution, Inc |
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IS25LP032D-RKLA3:P 数据表(HTML) 31 Page - Integrated Silicon Solution, Inc |
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31 / 118 page  IS25LP032D IS25WP032D Integrated Silicon Solution, Inc.- www.issi.com 31 Rev. A12 08/04/2020 8. DEVICE OPERATION The device utilizes an 8-bit instruction register. Refer to Table 8.1. Instruction Set for details on instructions and instruction codes. All instructions, addresses, and data are shifted in with the most significant bit (MSB) first on Serial Data Input (SI) or Serial Data IOs (IO0, IO1, IO2, IO3). The input data on SI or IOs is latched on the rising edge of Serial Clock (SCK) for normal mode and both of rising and falling edges for DTR mode after Chip Enable (CE#) is driven low (VIL). Every instruction sequence starts with a one-byte instruction code and is followed by address bytes, data bytes, or both address bytes and data bytes, depending on the type of instruction. CE# must be driven high (VIH) after the last bit of the instruction sequence has been shifted in to end the operation. Table 8.1 Instruction Set Instruction Name Operation Mode Byte0 Byte1 Byte2 Byte3 Byte4 Byte5 Byte6 NORD Normal Read Mode SPI 03h A <23:16> A <15:8> A <7:0> Data out FRD Fast Read Mode SPI QPI 0Bh A <23:16> A <15:8> A <7:0> Dummy(1) Byte Data out FRDIO Fast Read Dual I/O SPI BBh A <23:16> Dual A <15:8> Dual A <7:0> Dual AXh(1),(2) Dual Dual Data out FRDO Fast Read Dual Output SPI 3Bh A <23:16> A <15:8> A <7:0> Dummy(1) Byte Dual Data out FRQIO Fast Read Quad I/O SPI QPI EBh A <23:16> Quad A <15:8> Quad A <7:0> Quad AXh(1), (2) Quad Quad Data out FRQO Fast Read Quad Output SPI 6Bh A <23:16> A <15:8> A <7:0> Dummy(1) Byte Quad Data out FRDTR Fast Read DTR Mode SPI QPI 0Dh A <23:16> A <15:8> A <7:0> Dummy(1) Byte Dual Data out FRDDTR Fast Read Dual I/O DTR SPI BDh A <23:16> Dual A <15:8> Dual A <7:0> Dual AXh(1), (2) Dual Dual Data out FRQDTR Fast Read Quad I/O DTR SPI QPI EDh A <23:16> A <15:8> A <7:0> AXh(1), (2) Quad Quad Data out PP Input Page Program SPI QPI 02h A <23:16> A <15:8> A <7:0> PD (256byte) PPQ Quad Input Page Program SPI 32h 38h A <23:16> A <15:8> A <7:0> Quad PD (256byte) SER Sector Erase SPI QPI D7h 20h A <23:16> A <15:8> A <7:0> BER32 (32KB) Block Erase 32Kbyte SPI QPI 52h A <23:16> A <15:8> A <7:0> BER64 (64KB) Block Erase 64Kbyte SPI QPI D8h A <23:16> A <15:8> A <7:0> CER Chip Erase SPI QPI C7h 60h WREN Write Enable SPI QPI 06h WRDI Write Disable SPI QPI 04h RDSR Read Status Register SPI QPI 05h SR WRSR Write Status Register SPI QPI 01h WSR Data |
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