IS25LP032D-RKLA3:P datasheet(38/118 Pages) ISSI

38 / 118 page

IS25LP032D

IS25WP032D

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A12

08/04/2020

8.3 HOLD OPERATION

HOLD# is used in conjunction with CE# to select the device. When the device is selected and a serial sequence is

underway, HOLD# can be used to pause the serial communication with the master device without resetting the

serial sequence. To pause, HOLD# is brought low while the SCK signal is low. To resume serial communication,

HOLD# is brought high while the SCK signal is low (SCK may still toggle during HOLD). Inputs to SI will be ignored

while SO is in the high impedance state, during HOLD.

Note: HOLD# is not supported in DTR mode or with QE=1 or when RESET# is selected for the HOLD# or RESET# pin.

Timing graph can be referenced in AC Parameters Figure 9.4.

8.4 FAST READ DUAL I/O OPERATION (FRDIO, BBh)

The FRDIO allows the address bits to be input two bits at a time. This may allow for code to be executed directly

from the SPI in some applications.

The FRDIO instruction code is followed by three address bytes (A23

– A0) and dummy cycles (configurable, default

is 4 clocks), transmitted via the IO1 and IO0 lines, with each pair of bits latched-in during the rising edge of SCK.

The address MSB is input on IO1, the next bit on IO0, and this shift pattern continues to alternate between the two

lines. Depending on the usage of AX read operation mode, a mode byte may be located after address input.

The first data byte addressed is shifted out on the IO1 and IO0 lines, with each pair of bits shifted out at a maximum

frequency fCT, during the falling edge of SCK. The MSB is output on IO1, while simultaneously the second bit is

output on IO0. Figure 8.4 illustrates the timing sequence.

The first byte addressed can be at any memory location. The address is automatically incremented by one after

each byte of data is shifted out. When the highest address is reached, the address counter will roll over to the

000000h address, allowing the entire memory to be read with a single FRDIO instruction. FRDIO instruction is

terminated by driving CE# high (VIH).

The device supports the AX read operation by applying mode bits during dummy period. Mode bits consist of 8

bits, such as M7 to M0. Four cycles after address input are reserved for Mode bits in FRDIO execution. M7 to M4

are important for enabling this mode.

M3 to M0 become don’t care for future use. When M[7:4]=1010(Ah), it enables

the AX read operation and subsequent FRDIO execution skips command code. It saves cycles as described in

Figure 8.5. When the code is different from AXh (

where X is don’t care), the device exits the AX read operation.

After finishing the read operation, device becomes ready to receive a new command. SPI or QPI mode configuration

retains the prior setting. Mode bit must be applied during dummy cycles. Number of dummy cycles in Table 6.11

includes number of mode bit cycles. If dummy cycles are configured as 4 cycles, data output will start right after

mode bit is applied.

If the FRDIO instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the instruction is

ignored and will not affect the current cycle.

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