IS25LP032D-RKLA3:P datasheet(41/118 Pages) ISSI

41 / 118 page

IS25LP032D

IS25WP032D

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A12

08/04/2020

8.5 FAST READ DUAL OUTPUT OPERATION (FRDO, 3Bh)

The FRDO instruction is used to read memory data on two output pins each at up to a 133MHz clock.

The FRDO instruction code is followed by three address bytes (A23

– A0) and dummy cycles (configurable, default

is 8 clocks), transmitted via the IO0 line, with each bit latched-in during the rising edge of SCK. Then the first data

byte addressed is shifted out on the IO1 and IO0 lines, with each pair of bits shifted out at a maximum frequency

fCT, during the falling edge of SCK. The first bit (MSB) is output on IO1. Simultaneously, the second bit is output

on IO0.

The first byte addressed can be at any memory location. The address is automatically incremented by one after

each byte of data is shifted out. W hen the highest address is reached, the address counter will roll over to the

000000h address, allowing the entire memory to be read with a single FRDO instruction. The FRDO instruction is

terminated by driving CE# high (VIH).

If the FRDO instruction is issued while an Erase, Program or Write cycle is in process (BUSY=1) the instruction is

ignored and will not have any effects on the current cycle.

Figure 8.6 Fast Read Dual Output Sequence

CE #

SCK

Data Out 1

Instruction = 3Bh

CE #

SCK

3-byte Address

High Impedance

...

Mode 3

Mode 0

...

IO0

IO1

...

Data Out 2

IO0

IO1

8 Dummy Cycles

Note: Dummy cycles depends on Read Parameter setting. Detailed information in Table 6.11 Read Dummy Cycles.

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