MWCT1014AFVLLPR datasheet(30/65 Pages) NXP

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Table 21. Flash command timing specifications (continued)

Symbol

Description1

MWCT1014S

MWCT1015S

MWCT1016S

Typ

Max

Typ

Max

Typ

Max

Unit

Notes

complete, ready for

next 32-bit write)

Last (Nth) 32-

bit write (time

for write only,

not cleanup)

200

550

200

550

200

550

tquickwrClnup

Quick Write

Cleanup execution

time

—

(# of

Quick

Writes ) *

2.0

—

(# of

Quick

Writes )

* 2.0

—

(# of

Quick

Writes )

* 2.0

1. All command times assumes 25 MHz or greater flash clock frequency (for synchronization time between internal/external

clocks).

2. Maximum times for erase parameters based on expectations at cycling end-of-life.

3. For all EEPROM Emulation terms, the specified timing shown assumes previous record cleanup has occurred. This may

be verified by executing FCCOB Command 0x77, and checking FCCOB number 5 contents show 0x00 - No EEPROM

issues detected.

4. 1st time EERAM writes after a Reset or SETRAM may incur additional overhead for EEE cleanup, resulting in up to 2× the

times shown.

5. Only after the Nth write completes will any data be valid. Emulated EEPROM record scheme cleanup overhead may occur

after this point even after a brownout or reset. If power on reset occurs before the Nth write completes, the last valid record

set will still be valid and the new records will be discarded.

6. Quick Write times may take up to 550 µs, as additional cleanup may occur when crossing sector boundaries.

7. Time for emulated EEPROM record scheme overhead cleanup. Automatically done after last (Nth) write completes,

assuming still powered. Or via SETRAM cleanup execution command is requested at a later point.

NOTE

Under certain circumstances FlexMEM maximum times may be

exceeded. In this case the user or application may wait, or assert

reset to the FTFC macro to stop the operation.

6.3.1.2 Reliability specifications

Table 22. NVM reliability specifications

Symbol

Description

Min.

Typ.

Max.

Unit

Notes

When using as Program and Data Flash

tnvmretp1k Data retention after up to 1 K cycles

—

years

nnvmcycp

Cycling endurance

1 K

—

cycles

2, 3

When using FlexMemory feature: FlexRAM as Emulated EEPROM

tnvmretee

Data retention

—

years

nnvmwree16

nnvmwree256

Write endurance

• EEPROM backup to FlexRAM ratio = 16

• EEPROM backup to FlexRAM ratio = 256

100 K

1.6 M

—

writes

5, 6, 7

1. Data retention period per block begins upon initial user factory programming or after each subsequent erase.

2. Program and Erase for PFlash and DFlash are supported across product temperature specification in Normal Mode (not

supported in HSRUN mode).

3. Cycling endurance is per DFlash or PFlash Sector.

4. Data retention period per block begins upon initial user factory programming or after each subsequent erase. Background

maintenance operations during normal FlexRAM usage extend effective data retention life beyond 5 years.

Memory and memory interfaces

MWCT101XS Data Sheet, Rev. 3, 12/2019

NXP Semiconductors

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