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MWCT1014AFVLLPR 数据表(PDF) 6 Page - NXP Semiconductors |
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MWCT1014AFVLLPR 数据表(HTML) 6 Page - NXP Semiconductors |
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6 / 65 page ![]() EEPROM emulated by FlexRAM1 FlexRAM (also available as system RAM) Cache System RAM (including FlexRAM) Flash Single supply voltage Watchdog Number of I/Os Memory protection unit Parameter Peripheral speed CRC module IEEE-754 FPU Core EWM DMA Crossbar ISO 26262 HW security module (CSEc)1 Frequency Error correction code (ECC) Low power timer (LPTMR) Low power interrupt timer LEGEND: Not implemented Available on the device 1 No write or erase access to Flash module, including Security (CSEc) and EEPROM commands, are allowed when device is running at HSRUN mode (112MHz) or VLPR mode. 2 Option with No CSEc and CAN-FD is also available for MWCT1015S 3 Available when EEEPROM, CSEc and Data Flash are not used. Else only up to 1,984 KB is available for Program Flash. 4 4 KB (up to 512 KB D-Flash as a part of 2M Flash). Up to 64 KB of flash is used as EEPROM backup and the remaining 448 KB of the last 512 KB block can be used as Data flash or Program flash. See chapter FTFC for details. 5 Only for Boundary Scan Register 6 See Dimensions for package drawing Trigger mux (TRGMUX) Real time counter (RTC) FlexTimer (16-bit counter) 8 channels External memory interface 12-bit SAR ADC (1 MSPS each) FlexIO (8 pins configurable as UART, SPI, I2C, I2S) Low power I2C Debug & trace Packages6 Ecosystem (IDE, compiler, debugger) FlexCAN (CAN-FD ISO/CD 11898-1) Low power SPI Comparator with 8-bit DAC Programmable delay block (PDB) MWCT101xS MWCT1014S MWCT1015S MWCT1016S 1x SWD, JTAG5 (ITM, SWV, SWO) NXP S32 Design Studio + GCC + GHS + Lauterbach LQFP-64 LQFP-100 SWD, JTAG (ITM, SWV, SWO), ETM 1x (64) 2x (16) 2x (24) 2x (32) 3x 1x 2x 3x2 (2x with FD) 3x (3x with FD) 3x (1x with FD) 1x 1x (73) 1x (81) up to 112 MHz (HSRUN) 1x Arm® Cortex ™-M4F 1x capable up to ASIL-B up to 112 MHz (HSRUN) 4 KB (up to 64 KB D-Flash) 4 KB 4 KB 64 KB 128 KB 256 KB -40 to +105ºC / +125ºC 512 KB 1 MB 2 MB3 2.7 - 5.5 V up to 89 up to 89 up to 89 1x 1x 1x 4x (32) 6x (48) 8x (64) QuadSPI incl. HyperBus™ 2x Operating temperature (Ta) Temperature ambient FIRC CMU Low power modes LQFP-100 BGA-100 BGA-100 See footnote 4 Low power UART/LIN (Supports LIN protocol versions 1.3, 2.0, 2.1, 2.2A and SAE J2602) 3x HSRUN mode1 2 Figure 2. MWCT101xS product series comparison Feature comparison MWCT101XS Data Sheet, Rev. 3, 12/2019 6 NXP Semiconductors |
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