
DM560P
V.90 Integrated Data/Fax/Voice/Speakerphone Modem Device Set
28
Preliminary
Version: DM560P-DS-P07
August 11, 2000
DM6581/82 Pin Description
Pin No.
Pin Name
I/O
Description
1
RD_SP2
I
Data Input Pin Of Serial Port 2:
The serial data is sampled at the falling edge of the SCLK. The
MSB is coming immediately after falling of FR_SP2 signal.
2
FR_SP2
I/O
Frame Signal For Serial Port 2:
This pin is used to indicate a data transfer. It remains in a low
state until the rising edge of SCLK is detected. A high to low
transition initiates a data transfer.
3
AVDD
P
Analog Power For PLL Circuit
4OSCO
O
Oscillator Output Pin
5OSCI
I
Oscillator Input Pin:
A 40.32MHz crystal and feedback resister should be connected
between OCSI and OSCO.
8AGND
P
Analog Ground For PLL Circuit
7
TXDCLK
I
Transmit Data Rate Clock:
This pin is used as reference clock of TXD pin.
6, 29, 60, 68, 71,
84, 94, 95
DGND
P
Digital Ground
9
RXDCLK
I
Receive Data Rate Clock:
This pin is used as reference clock of RXD pin.
10
CODEC_CLK
O
20.16MHz Clock Output For DM6580 Chip
11
RXD
O
Modem Received Data
Shifted out to the EIA port through this pin according to the rising
edge of RXDCLK.
12, 42, 57, 90
VDD
P
Digital Power
13
TXD
I
Modem Transmit Data
Shifted into DM6581/DM6582 from EIA port through this pin at the
rising edge of TXDCLK.
14
/URD
I
Read Indication Of Dual Port RAM, low active.
15
/UWR
I
Write Indication Of Dual Port RAM, low active.
16 - 19
UAR3 - UAR0
I
Dual Port RAM Address Bus Input
This address bus can access 16 bytes dual port RAM.
20
/UCS
I
Dual Port RAM Chip Select Pin, low active.
21 - 28
UD0 - UD7
I/O
Data Bus Of The Dual Port RAM
30
MSCLK
O
Clock Output Pin
The frequency of this clock 40.32MHz.
31
P0.F
O
Output Port Bit F
32
Eye_SD
O
Output Pin for Eye Pattern
33
Eye_FR
O
Output Pin for Frame Signal of Eye Pattern
34
P0.C
O
Output Port Bit C
35 - 41, 43 - 56,
58, 59, 61 - 67,
70, 72, 77 - 83,
85 - 89
NC
-
No Connection