DM560P
V.90 Integrated Data/Fax/Voice/Speakerphone Modem Device Set
Preliminary
9
Version: DM560P-DS-P07
August 11, 2000
UART Clock
The internal clock of the virtual UART logic is fixed at
1.8432MHz. The clock is derived from the MSCLK
signal from the DM6582 DSP, or an external 30Mhz
crystal. The UART 1.8432MHz clock will be obtained
by division. When the operating frequency of the
DM6583 controller changes, the divider should be
changed accordingly. This divider is specified by the
Configuration Register which can be written by the
DM6583 controller. The address mapping of the
register is D400H: (DM6583 controller memory
mapping)
Bit 0: Always 0.
Bit 6-1: define the clock divider range from 2 to 64
(even number).
Bit 7: Not used.
UART Baud Generator Divisor Latch Register:
Address EC00H
Read only
bit7
bit6
bit5
bit4
bit3
bit2
bit1 bit0
dat7 dat6 dat5 dat4 dat3 dat2 dat1 dat0
By reading this register, the micro-controller can
monitor the value of the low byte divisor latch of the
virtual UART baud generator (see DLL in next
section) and determine the baud rate clock itself.
Modem Status Control Register (MSCR):
Address E000H
Write only
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
0000/CTS /DSR /DCD
/RI
This register contains information about the line
status of the modem. The available signals are Ring
Detect (/RI), Carrier Detect (/DCD), Data Set Ready
(/DSR) and Clear To Send (/CTS).
Modem Output Port Register: Address D000H
Write only
bit7
bit6
bit5
bit4 bit3
bit2
bit1
bit0
/Voice Voice
-sel2
Voice
-Sel1
/POR
These 4 bits control the DM6583 output ports.
PnP Isolation & Resource Data Port: Address
F800H
Write only
The PnP isolation and resource data can be byte-
sequentially written to the corresponding memory
through this register.
Auto-configuration Register: Address F400H
bit2 bit1 bit0 IRQ bit5 bit4 bit3 I/O
0
0
0
3
0
0
0
03F8-03FF(COM1)
0
0
1
4
0
0
1
02F8-02FF(COM2)
0
1
0
5
0
1
0
03E8-03EF(COM3)
0
1
1
7
0
1
1
02E8-02EF(COM4)
1
0
0
10
1
0
0
03F0-03F7(COM5)
1
0
1
11
1
0
1
02F0-02F7(COM6)
1
1
0
12
1
1
0
03E0-03E7(COM7)
1
1
1
15
1
1
1
02E0-02E7(COM8)
The default I/O base and IRQ data stored in 93C46 is
loaded to this register by the micro-controller. The
micro-controller can also get the current I/O base
and IRQ information settings by performing a read
from this register. The configuration determined by
this register will be disabled when the register
detects the Initiation Key described in the next
section.
Bit 6: This bit is set to inform micro-controller that the
current I/O base and IRQ data should be stored to
93C46 as the default setting for the next power-on
reset through programming the Auto-configuration
Register. This bit will be cleared by micro-controller.
Bit 7: When bit 7 is set, it enables the hardware
configuration to be set according to bit 0-bit 5
(Jumperless mode) and loads the proper value into
the PnP Registers including I/O and Interrupt
Configuration Registers. This bit will be reset, when it
receives PnP Initiation Key sequence.
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