DM560P
V.90 Integrated Data/Fax/Voice/Speakerphone Modem Device Set
Preliminary
35
Version: DM560P-DS-P07
August 11, 2000
DM6580 Pin Description
Pin No.
Pin Name
I/O
Description
1
RXDCLK
O
Receive Data Clock
2VDD
P
Digital Power
3
RXSCLK
O
Receive Sample Clock
4
RFS
I
Receive Frame Synchronization
5
DOR
O
Data Output For Receiver
6
DIR
I
Data Input For Receiver
7
DGND
P
Digital Ground
8
SCLK
O
Serial Clock Synchronized With All Serial Data
9
DOT
O
Data Output For Transmitter
10
DIT
I
Data Input For Transmitter
11
TFS
I
Transmit Frame Synchronization
12
TXSCLK*2
O
Transmit Sample Clock * 2
13
TXDCLK
O
Transmit Data Clock
14
CLKIN
I
Master Clock Input (20.16MHz = 40.32MHz / 2 )
15
/RESET
I
Codec Reset Input
16
EXTCLK
I
External Transmit Data Clock
17
Vr
O
Internal Reference Voltage. Connect 0.1uF to DGND
18
AVDDT
I
Analog VDD For The Transmitter Analog Circuitry (+5VDC)
19
TXA2
O
Transmit Negative Analog Output
20
TXA1
O
Transmit Positive Analog Output
21
AGNDR
P
Analog Receiver Circuitry Signal Return Path
22
VREFN
O
Negative Reference Voltage, VCM - 1V
23
VCM
O
Common Mode Voltage Output, 2.5V
24
VREFP
O
Positive Reference Voltage, VCM + 1V
25
AGNDT
P
Analog Transmitter Circuitry Signal Return Path
26
RXIN
I
Receive Analog Input
27
AVDDR
I
Analog VDD For The Receiver Analog Circuitry (+5VDC)
28
SPKR
O
Speaker Driver
DM6580 Functional Description
In this chip, we could roughly divide it into two major
parts : digital portion and analog portion. The
functional blocks are described separately in this
section. The analog circuits include a sigma-delta
modulator/demodulator, decimation/interpolation
filters, a speaker driver, low-pass filter and certain
logic circuits. The digital circuits is composed of Tx/Rx
clock generator/PLL, serial port, serial/parallel
conversions and control registers. All the clock
information the analog circuits need should be
provided by the digital clock system since the best
sampling instant of A/D and D/A depends on the
received signal and transmit signals. The data format
of A/D and D/A is 2's complement.
The master clock (FQ) is obtained from an external
signal connected to CLKIN. The different transmit and
receive clocks are obtained by master clock frequency
division in several programmable counters. The Tx
and Rx clocks can be synchronized on external
signals by performing the phase shifts in the frequency
division process. Two independent digital phase
locked loops are implemented using this principle, one
for transmit clock system, the other, receive clock. The
tracking of the transmit clock is automatically done by
the transmit DPLL circuit. The receive DPLL circuit is
controlled by the host processor and it is actually an
adjustable phase shifter.
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