DM560P
V.90 Integrated Data/Fax/Voice/Speakerphone Modem Device Set
30
Preliminary
Version: DM560P-DS-P07
August 11, 2000
Dual Port RAM
The 16 X 8 dual port RAM allows easy system
expansion by adding another DSP or micro-processor.
Address 2000h ~ 200Fh are reserved for this dual port
RAM. The 8 bit dual port RAM data corresponds to the
MSBs of the data bus (bit 15 ~ bit 8) of the DSP core.
Upon reading the dual port RAM, the 8 LSB contents
(bit 7 to bit 0) are all 0. For the convenience of
description, the micro-controller port is referred to as B
port and the DSP port is referred to as A port.
Interrupt
The DSP core provides 4 nested interrupt inputs:
IRQ3, IRQ2, IRQ1, IRQ0. IRQ3 is the highest priority
input and IRQ0, the lowest. In the V.90 and V.32
application, the IRQ3, IRQ2 and IRQ1 are defined as
external interrupts triggered from the pin IRQ3B,
IRQ2B, IRQ1B respectively.
CoProcessor
The coprocessor is implemented to provide the
functions of echo cancellation for the DM6581
(TXDSP) and adaptive equalization for the DM6582
(RXDSP).
Power Down Mode
Power Down mode is selected by bit 7 in register E.
This bit is write-only and can only be accessed by the
controller. Power Down mode is entered by setting the
PWD bit. A reset must occur to return to normal
operation.
PWD = 0: Normal Operation
PWD = 1: Power Down Mode.
Bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
PWD
Bit6
Bit5
Bit4 Mode Bit2
Bit1
F-
Empty
Eye Pattern Registers
The Eye Pattern Registers are memory mapped as
shown below.
Address
Symbol
R/W
3000
Eye_X_Reg
W
3001
Eye_Y_Reg
W
When data is loaded into the Eye_Y_Reg the Eye_FR
pin will be driven low for 16 SCLK periods. The
contents on the Eye_X/Y_Reg will be shifted out on
the Eye_SD pin on the rising edge of SCLK when
Eye_FR is Low.
DM6581/82 Functional Description (continued)
Eye Pattern Timings
Eye_FR
Eye_SD
1
2
SCLK
Symbol
Parameter
Min.
Typ.
Max.
Unit
Conditions
1
Eye_FR active after SCLK High
0
20
ns
2
Eye_FR active after SCLK High
0
20
ns
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