STM32WLE4JC datasheet(16/145 Pages) STMICROELECTRONICS

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Functional overview

STM32WLE5/E4xx

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DS13105 Rev 8

The MPU is especially helpful for applications where some critical or certified code must be

protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-

time operating system). If a program accesses a memory location that is prohibited by the

MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can

dynamically update the MPU area setting, based on the process to be executed.

The MPU is optional and can be bypassed for applications that do not need it.

3.5

Memories

3.5.1

Embedded Flash memory

The Flash memory interface manages the accesses from CPU AHB ICode/DCode to the

Flash memory. It implements the access, the erase and program Flash memory operations,

and the read and write protection.

The main features of the Flash memory are listed below:

•

Memory organization: 1 bank

–

main memory: up to 256 Kbytes

–

page size: 2 Kbytes

•

72-bit wide data read (64 bits plus 8 ECC bits)

•

72-bit wide data write (64 bits plus 8 ECC bits)

•

Page erase and mass erase

Flexible protections can be configured thanks to option bytes:

•

Readout protection (RDP) to protect the whole memory. Three levels are available:

–

Level 0: no readout protection

–

Level 1: memory readout protection. The Flash memory cannot be read from or

written to if either debug features are connected, boot in SRAM or bootloader is

selected.

–

Level 2: chip readout protection. Debug features (JTAG and serial wire), boot in

SRAM and bootloader selection are disabled (JTAG fuse). This selection is

irreversible.

Table 3. Access status versus RDP level and execution mode

Area

RDP

level

User execution

Debug, boot from SRAM or boot from

system memory (loader)

Read

Write

Erase

Read

Write

Erase

Main memory

Yes

System memory

1Yes

Yes

Option bytes

Yes

2Yes

No(1)

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