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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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STPMIC1APQR 数据表(PDF) 82 Page - STMicroelectronics |
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STPMIC1APQR 数据表(HTML) 82 Page - STMicroelectronics |
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82 / 140 page  6.3.8 Mask reset Buck control register (BUCKS_MRST_CR) Table 32. BUCKS_MRST_CR 7 6 5 4 3 2 1 0 reserved reserved reserved reserved MRST_BUCK4 MRST_BUCK3 MRST_BUCK2 MRST_BUCK1 R/W R/W R/W R/W R/W R/W R/W R/W Address: 0x18 Type: read/write register Default: 0x00 Description: mask reset Buck control register. Set bit to 1 active Mask reset option for selected Bucks for the next NRST power cycle. It is a single shot option. Register is reset to default in CHECK&LOAD state. Refer to Section 5.4.4 Reset and mask_reset option. [7 :4] Reserved [3] MRST_BUCK4: Buck 4 mask reset option 0: inactive 1: Mask default active for Buck4 [2] MRST_BUCK3: Buck3 mask reset option 0: inactive 1: Mask default active for Buck3 [1] MRST_BUCK2: Buck2 mask reset option 0: inactive 1: Mask default active for Buck2 [0] MRST_BUCK1: Buck1 mask reset option 0: inactive 1: Mask default active for Buck1 STPMIC1 Control registers DS12792 - Rev 7 page 82/140 |
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