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数据搜索系统，热门电子元器件搜索 |
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STPMIC1APQR 数据表(PDF) 90 Page - STMicroelectronics |
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STPMIC1APQR 数据表(HTML) 90 Page - STMicroelectronics |
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90 / 140 page  6.4.3 LDOx MAIN mode control registers (LDOx_MAIN_CR) (x=1, 2, 5, 6) Table 40. LDOx_MAIN_CR 7 6 5 4 3 2 1 0 reserved VOUT[4:0] Reserved ENA R/W R/W R/W R/W R/W R/W R/W R/W Address: 0x25, 0x26, 0x29, 0x2A Type: read/write register Default: 0b0XXXXX00 where X depends on the value programmed in NVM Description: LDOx (x=1,2,5,6) MAIN mode control register. The register is set to default value in CHECK&LOAD. User can write to this register to control both enable and voltage settings of LDOx that are applied to MAIN mode. [7] Reserved [6:2] VOUT[4:0]: refer to Table 9. LDO output voltage settings [1] reserved [0] ENA: LDOx enable bit 0: LDOx is disabled 1: LDOx is enabled STPMIC1 Power supplies control registers DS12792 - Rev 7 page 90/140 |
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