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STPMIC1APQR 数据表(PDF) 91 Page - STMicroelectronics |
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STPMIC1APQR 数据表(HTML) 91 Page - STMicroelectronics |
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91 / 140 page  6.4.4 LDO3 MAIN mode control register (LDO3_MAIN_CR) Table 41. LDO3_MAIN_CR 7 6 5 4 3 2 1 0 BYPASS VOUT[4:0] reserved ENA R/W R/W R/W R/W R/W R/W R/W R/W Address: 0x27 Type: read/write register Default: 0bXXXXXX00 where X depends on the value programmed in NVM Description: LDO3 MAIN mode control register. The register is set to a default value in CHECK&LOAD. User can write to this register to control bypass, enable and voltage settings of LDO3 that is applied to MAIN mode. [7] BYPASS: force bypass mode of LDO3 0: LDO3 is in normal mode 1: LDO3 is in bypass mode. VOUT[4:0] bits have no effect [6:2] VOUT[4:0]: refer to Table 9. LDO output voltage settings [1] reserved [0] ENA: LDO3 enable bit 0: LDO3 is disabled 1: LDO3 is enabled STPMIC1 Power supplies control registers DS12792 - Rev 7 page 91/140 |
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