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STPMIC1APQR 数据表(PDF) 107 Page - STMicroelectronics |
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STPMIC1APQR 数据表(HTML) 107 Page - STMicroelectronics |
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107 / 140 page  6.5.9 Interrupt set mask registers (INT_SET_MASK_Rx) Table 56. INT_SET_MASK_Rx Name Address 7 6 5 4 3 2 1 0 INT_SET _MASK_R1 0x90 SWOUT _RI SWOUT _FA VBUS OTG_RI VBUSOTG _FA WKP _RI WKP _FA PKEY _RI PKEY _FA INT_SET _MASK_R2 0x91 BST _OVP BST _OCP SWOUT _OCP VBUS OTG_OCP BUCK4_ OCP BUCK3_ OCP BUCK2_ OCP BUCK1_ OCP INT_SET _MASK_R3 0x92 SWOUT _SH VBUS OTG_SH LDO6_ OCP LDO5_ OCP LDO4_ OCP LDO3_ OCP LDO2_ OCP LDO1_ OCP INT_SET _MASK_R4 0x93 SWIN _RI SWIN _FA reserved reserved VINLOW _RI VINLOW _FA THW _RI THW _FA Address: 0x90 – 0x93 Type: write registers - read x00 Default: 0x00 Description: interrupt set mask registers. Registers are default on RSTn assertion Writing 1 in the bit forces the mask of the corresponding interrupt event in INT_MASK_Rx Refer to Section 6.5.2 Interrupt pending register 1 (INT_PENDING_R1), Section 6.5.3 Interrupt pending register 2 (INT_PENDING_R2), Section 6.5.4 Interrupt pending register 3 (INT_PENDING_R3) and Section 6.5.5 Interrupt pending register 4 (INT_PENDING_R4) about the interrupt description. STPMIC1 Interrupt registers DS12792 - Rev 7 page 107/140 |
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