STPMIC1APQR datasheet(123/140 Pages) STMICROELECTRONICS

部件名	STPMIC1APQR

功能描述	Highly integrated power management IC for micro processor units

PDF	140 Pages

Scroll/Zoom	100%

制造商	STMICROELECTRONICS [STMicroelectronics]

网页	http://www.st.com

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123 / 140 page

6.7.6

NVM LDOs voltage output shadow register 1 (NVM_LDOS_VOUT_SHR1

Table 70. NVM_LDOS_VOUT_SHR1

SWOUT_BOOST_OVP

reserved

LDO3_VOUT[1:0]

LDO2_VOUT[1:0]

LDO1_VOUT[1:0]

R/W

Address: 0xFD

Type: read write register

Default: depends on part number refer to Table 64. NVM shadow register map

Description: NVM LDO1 to LDO3 default voltage output setting shadow register.

[7]

SWOUT_BOOST_OVP:

0: PWR_SW does not turn OFF if boost OVP occurs

1: PWR_SW is turned OFF automatically if Boost OVP occurs

[6]

reserved

[5:4]

LDO3_VOUT[1:0]: LDO3 default output selection

00: 1.8 V

01: 2.5 V

10: 3.3 V

11: VOUT[5:0] of Buck2 divided by 2

[3:2]

LDO2_VOUT[1:0]: LDO2 default output selection

00: 1.8 V

01: 2.5 V

10: 2.9 V

11: 3.3 V

[1:0]

LDO1_VOUT[1:0]: LDO1 default output selection

00: 1.8 V

01: 2.5 V

10: 2.9 V

11: 3.3 V

STPMIC1

NVM shadow registers

DS12792 - Rev 7

page 123/140

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