STPMIC1APQR datasheet(138/140 Pages) STMICROELECTRONICS

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List of figures

Figure 1.

Typical application schematic .......................................................... 3

Figure 2.

Pin configuration WFQFN 44L top view ................................................... 5

Figure 3.

BUCK1 efficiency ................................................................. 22

Figure 4.

BUCK2 efficiency ................................................................. 22

Figure 5.

BUCK3 efficiency ................................................................. 22

Figure 6.

BUCK4 efficiency ................................................................. 22

Figure 7.

Boost efficiency .................................................................. 22

Figure 8.

Boost powered by 5 V supply having poor performance ....................................... 22

Figure 9.

BUCK1 load transient in HP mode ..................................................... 23

Figure 10.

Buck1 load transient in LP mode....................................................... 23

Figure 11.

BUCK2 load transient in HP mode ..................................................... 23

Figure 12.

Buck2 load transient in LP mode....................................................... 23

Figure 13.

Buck3 load transient in HP mode ...................................................... 23

Figure 14.

Buck3 load transient in LP mode....................................................... 23

Figure 15.

Buck4 load transient in HP mode ...................................................... 23

Figure 16.

Buck4 load transient in LP mode....................................................... 23

Figure 17.

LDO1 load transient ............................................................... 24

Figure 18.

LDO2 load transient ............................................................... 24

Figure 19.

LDO3 load transient ............................................................... 24

Figure 20.

LDO4 load transient ............................................................... 24

Figure 21.

LDO5 load transient ............................................................... 24

Figure 22.

LDO6 load transient ............................................................... 24

Figure 23.

LDO4 line transient ................................................................ 24

Figure 24.

Boost output vs. input voltage......................................................... 24

Figure 25.

Boost load regulation 5 VIN .......................................................... 25

Figure 26.

Boost load regulation 3.6 VIN ......................................................... 25

Figure 27.

LDO1 line transient, no load .......................................................... 25

Figure 28.

LDO2 line transient, no load .......................................................... 25

Figure 29.

LDO3 line transient, no load .......................................................... 25

Figure 30.

LDO5 line transient, no load .......................................................... 25

Figure 31.

LDO6 line transient, no load .......................................................... 25

Figure 32.

LDO3 sink/source mode load transient response............................................ 25

Figure 33.

Buck1 turn-ON waveform ............................................................ 26

Figure 34.

STPMIC1A POWER_UP sequencing ................................................... 26

Figure 35.

STPMIC1A POWER_UP sequencing PONKEYn............................................ 26

Figure 36.

STPMIC1A POWER_DOWN sequencing................................................. 26

Figure 37.

STPMIC1A reset sequencing ......................................................... 26

Figure 38.

LDO start-up/shutdown timings ....................................................... 29

Figure 39.

Powering lpDDR2/lpDDR3 memory (LDO3 in bypass mode).................................... 32

Figure 40.

Powering lpDDR2/lpDDR3 memory (LDO3 normal mode supplied from VIN) ........................ 32

Figure 41.

Powering DDR3/DDR3L memory (LDO3 in sink/source mode) .................................. 33

Figure 42.

PWM clock generation.............................................................. 34

Figure 43.

PWM clock synchronisation .......................................................... 34

Figure 44.

Buck block diagram................................................................ 35

Figure 45.

BUCKx LP to HP mode recovery time ................................................... 36

Figure 46.

BUCKx start-up/shutdown timings ...................................................... 37

Figure 47.

BUCKx dynamic voltage scaling (DVS) .................................................. 37

Figure 48.

Boost and switch block diagram ....................................................... 40

Figure 49.

Boost start-up sequence ............................................................ 41

Figure 50.

Battery powered application with a USB OTG port and a USB host port ............................ 44

Figure 51.

Battery powered application with a single USB OTG port ...................................... 45

Figure 52.

5 V DC powered application with a USB OTG port and two USB host ports ......................... 46

STPMIC1

List of figures

DS12792 - Rev 7

page 138/140

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