Data Sheet

ADPA1105

Rev. 0 | Page 5 of 16

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

17

1

3

4

2

GND

NC

NC

RFIN

5

6

RFIN

GND

7

NC

8

GND

GND

18 NC

19 GND

20 RFOUT

21 RFOUT

22 NC

23 NC

24 GND

ADPA1105

TOP VIEW

(Not to Scale)

NOTES

1. THE NC PINS ARE NOT CONNECTED INTERNALLY.

HOWEVER, ALL DATA SHOWN IS MEASURED

WITH THE NC PINS CONNECTED TO RF AND DC

GROUND EXTERNALLY.

2. EXPOSED PAD. THE EXPOSED PAD MUST BE

CONNECTED TO RF AND DC GROUND.

Figure 2. Pin Configuration

Table 6. Pin Function Descriptions

Pin No.

Mnemonic

Description

1, 6, 8, 9, 16, 17, 19,

24, 25, 32

GND

The GND pins must be connected to RF and dc ground. See Figure 6 for the interface schematic.

2, 3, 7, 12, 13, 18, 22,

23, 26, 27, 29, 30

NC

The NC pins are not connected internally. However, all data shown is measured with the NC pins

connected to RF and dc ground externally.

4, 5

RFIN

RF Input. The RFIN pins are ac-coupled and are matched to 50 Ω. See Figure 3 for the interface schematic.

10

Gate Control, First Stage Gate Bias. See Figure 3 for the interface schematic.

11

Gate Control, Second Stage Gate Bias. See Figure 4 for the interface schematic.

14

VDET

Detector Diode to Measure RF Output Power. Output power detection via VDET requires the application

of a dc bias voltage through an external series resistor. Used in combination with the VREF pin, the

difference in voltage (VREF − VDET) is a temperature compensated dc voltage that is proportional to

the RF output power.

15

VREF

Reference Diode for Temperature Compensation of VDET RF Output Power Measurements. VREF

requires the application of a dc bias voltage through an external series resistor.

20, 21

RFOUT

RF Output. The RFOUT pins are ac-coupled and are matched to 50 Ω. See Figure 4 for the interface schematic.

28

Amplifier Power Supply Voltage, Second Stage Drain Bias. See Figure 4 for the interface schematic.

31

Amplifier Power Supply Voltage, First Stage Drain Bias. See Figure 3 for the interface schematic.

EPAD

Exposed Pad. The exposed pad must be connected to RF and dc ground.

INTERFACE SCHEMATICS

RFIN

RFOUT

VDET

VREF

Figure 5. VREF Interface

GND

Figure 6. GND Interface