Data Sheet

ADPA1105

Rev. 0 | Page 13 of 16

THEORY OF OPERATION

The ADPA1105 is a GaN power amplifier that delivers 46 dBm

(40 W) of pulsed power. The device consists of two cascaded

gain stages. A simplified view of this architecture is shown in

the basic block diagram in Figure 49.

The ADPA1105 has single-ended RFIN and RFOUT ports that

are dc blocked. The impedances of these ports are nominally

50 Ω over the 0.9 GHz to 1.6 GHz operating frequency range.

Consequently, the ADPA1105 can be directly inserted into a

50 Ω system without the need for external impedance matching

components or ac coupling capacitors.

the drains of the first and second gain stages, respectively (a single

common supply voltage must be used). The negative dc voltages

second gain stages, respectively, to allow control of the drain

currents for each stage (a single common gate voltage must

be used).

The recommended dc biasing results in a typical pulsed RF

output power and PAE of 46 dBm and 60%, respectively, at

1.5 GHz when the input power is 19 dBm.

A portion of the RF output signal is directionally coupled to a

diode to detect the RF output power. When the diode is dc biased,

the diode rectifies the RF power and makes the RF power

available for measurement as a dc voltage at the VDET pin. A

symmetrical diode circuit that is not coupled to the RF output,

which contains a dc voltage output at the VREF pin, is referenced

to accomplish temperature compensation. The difference of

VREF − VDET provides a temperature compensated signal that

is proportional to the RF output.

RFIN

RFOUT

VREF

VDET

DIRECTIONAL

COUPLER

Figure 49. Basic Block Diagram