数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

LTM4656 数据表(PDF) 4 Page - Analog Devices

部件名 LTM4656
功能描述  Synchronous Boost 關Module Regulator with Input-Output Short Protection
PDF  28 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

LTM4656 数据表(HTML) 4 Page - Analog Devices

  LTM4656 Datasheet HTML 1Page - Analog Devices LTM4656 Datasheet HTML 2Page - Analog Devices LTM4656 Datasheet HTML 3Page - Analog Devices LTM4656 Datasheet HTML 4Page - Analog Devices LTM4656 Datasheet HTML 5Page - Analog Devices LTM4656 Datasheet HTML 6Page - Analog Devices LTM4656 Datasheet HTML 7Page - Analog Devices LTM4656 Datasheet HTML 8Page - Analog Devices LTM4656 Datasheet HTML 9Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 4 / 28 page
background image
LTM4656/LTM4656-1
4
Rev. 0
For more information www.analog.com
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VRUN
RUN Pin ON Threshold
VRUN Rising
1.18
1.28
1.38
V
VRUNHYS
RUN Pin ON Hysteresis
100
mV
In-Line Protection Control Section
SHDN
Active Low Shutdown
4V to 36V Input
Threshold
l
0.6
0.385
1.4
1.7
2.1
V
V
SHDN Reset
SHDN Reset Time
SHDN = 0.4V (Note 6)
100
µs
UV Threshold
Undervoltage Lockout
UV Lockout Threshold, VIN =12V
l
1.24 1.275 1.31
V
UV Hysteresis
UV Input Hysteresis
VIN > 4.5V, Nominal 12V (Note 6)
12
mV
UV IN
UV Input Current
UV =1 .275V (Note 6)
l
±0.3
±1
µA
VTMR(F)
TMR Fault Threshold
TMR Rising (Note 6)
1.275
V
VTMR(G)
TMR Gate Off Threshold
TMR Rising
1.375
V
VTMR(H)
TMR Cooldown High Threshold
VIN = 12V to 24V, TMR Rising
4.3
V
TMR OVER I (5V)
TMR Overcurrent tVDS = 5V
VIN, SHDN, UV = 5V, VFB = 24.3k, 12V VOUT Shorted
800
µs
TMR OVER I (12V)
TMR Overcurrent tVDS = 12V
VIN, SHDN, UV =12V, VFB = 11.5k, 24V VOUT Shorted
220
µs
TMR OVER I (24V)
TMR Overcurrent tVDS = 24V
VIN, SHDN, UV = 24V, VFB = 7.5k, 36V VOUT Shorted
150
µs
ILEAK(FLT)
FLT Pin Leak
FLT = 36V
l
±2.5
µA
VIN – BVIN Rising Delta Path Fully Enhanced
Delta VIN – BVIN Enhancing, Boost RUN Pin Enabled l 0.25
0.5
0.75
V
VIN – BVIN Falling Delta Path Being Opened
Delta VIN – BVIN Opening, Boost RUN Pin Pulled Low
2.7
V
DC
Retry Duty Cycle, Shorted Output
VIN = 12V, VOUT = 0V, Referenced to BVIN
1
%
tOFF(UV)
Undervoltage Turn-Off Propagation Delay UV Steps from 1.5V to 1V (Note 6)
l
2
5
µs
VOL(FLT)
FLT Output Low
ISINK =100µA
l
0.3
0.8
V
PGOOD Output
VPGL
PGOOD Voltage Low
IPGOOD = 2mA
0.3
V
IPGOOD(LEAK)
PGOOD Leakage Current
VPGOOD = 6V
±1
μA
VPG
PGOOD Trip Level
VFB with Respect to Set Regulated Voltage
VFB Ramping Negative
VFB Ramping Positive
–12
8
–10
10
–8
12
%
%
ELECTRICAL CHARACTERISTICS The
l
denotes the specifications which apply over the specified operating
temperature range, otherwise specifications are at TA = 25°C. (Note 2), VIN = 12, VBIAS = BVIN, SHDN = VIN per the typical application,
or otherwise specified in the table.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTM4656 is tested under pulsed load conditions such
that TJ ≈ TA. The LTM4656E is guaranteed to meet performance
specifications over the 0°C to 125°C internal operating temperature
range. Specifications over the full –40°C to 125°C internal operating
temperature range are assured by design, characterization and correlation
with statistical process controls. The LTM4656I is guaranteed to meet
specifications over the full –40°C to 125°C internal operating temperature
range. Note that the maximum ambient temperature consistent with
these specifications is determined by specific operating conditions in
conjunction with board layout, the rated package thermal resistance and
other environmental factors.
Note 3: The minimum on-time condition is specified for a peak-to-
peak inductor ripple current of ~40% of IMAX Load. (See Applications
Information section)
Note 4: See output current derating curves for different VIN, VOUT and TA.
Note 5: Guaranteed by design.
Note 6: 100% tested at wafer level.
Note 7: JEDEC board θ values are determined by simulation per JESD51
conditions. Demo board θ values are obtained with demo board. Refer
to Figure 9 to Figure 17 and Table 2 to Table 5 for lab ameasurement and
derating information.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com