LTM4656 datasheet(16/28 Pages) AD

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LTM4656/LTM4656-1

Rev. 0

For more information www.analog.com

APPLICATIONS INFORMATION

The typical input clock thresholds on the MODE_PLLIN

pin are 1.6V (rising) and 1.2V (falling).

Overtemperature Protection

At higher temperatures, or in cases where the internal

power dissipation causes excessive self-heating of the

boost controller (such as an INTVCC short to ground),

the overtemperature shutdown circuitry will shut down

the boost converter. When the junction temperature ex-

ceedsapproximately170°C,theovertemperaturecircuitry

disables the INTVCC LDO, causing the INTVCC supply to

collapse and effectively shut down the entire boost con-

troller chip. Once the junction temperature drops back

to approximately 155°C, the INTVCC LDO turns back on.

Long-term overstress (TJ > 125°C) should be avoided as

it can degrade the performance or shorten life. As explain

aboveintheinlineprotection,ifanovercurrentshortoccurs

in the boost converter section, then the inline protection

will operate in a low duty cycle retry mode.

Thermal Performance

The LTM4656 provides adequate heat sinking utilizing the

inductor on top of package, and can either be cooled with

airflow or other heat sinking methods. Figure 7 shows a

12V to 24V boost at 96W conversion with only ~ 36°C

rise with 200LFM.

GND, tied to INTVCC, or programmed through an external

resistor. Tying FREQ to GND selects 350kHz while tying

FREQtoINTVCCselects535kHz.Placingaresistorbetween

FREQ and GND allows the frequency to be programmed

between 50kHz and 900kHz, as shown in Figure 6. The

recommendedoperatingrangefortheLTM4656is300kHz

to 780kHz based on the internal 4.7µH inductor.

A phase-locked loop (PLL) is available on the LTM4656’s

boost converter to synchronize the internal oscillator to an

externalclocksourcethatisconnectedtotheMODE_PLLIN

pin.TheLTM4656’sboostconverterphasedetectoradjusts

the voltage (through an internal low pass filter) of the VCO

input to align the turn-on of the external bottom MOSFET

to the rising edge of the synchronizing signal.

The VCO input voltage is pre-biased to the operating fre-

quency set by the FREQ pin before the external clock is

applied. If pre-biased near the external clock frequency,

the PLL loop only needs to make slight changes to the

VCO input in order to synchronize the rising edge of the

external clock’s to the rising edge of BG. The ability to

pre-bias the loop filter allows the PLL to lock-in rapidly

without deviating far from the desired frequency.

TheMODE_PLLINisguaranteedtolocktoanexternalclock

source whose frequency is between 75kHz and 850kHz.

Figure 6. Relationship Between Oscillator

Frequencies and Resistor Value at the FREQ Pin

FREQ PIN RESISTOR (k)

600

800

1000

35 45 55

4656 F06

400

200

500

700

900

300

100

65 75 85 95 105 115 125

Figure 7. 12VIN to 24VOUT at 4A (96W),

200LFM Air Flow Thermal Plot

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