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数据搜索系统，热门电子元器件搜索 |
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AM79C02AJC 数据表(PDF) 17 Page - Advanced Micro Devices |
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AM79C02AJC 数据表(HTML) 17 Page - Advanced Micro Devices |
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17 / 48 page  SLAC Products 17 SWITCHING CHARACTERISTICS over operating range unless otherwise noted Microprocessor Interface Min and max values are valid for all digital outputs with a 150 pF load, except C1–C5 with a 30 pF load. Pull-up resistors of 360 Ω are attached to TSCA and TSCB. PCM Interface PCLK not to exceed 4.096 MHz when PCM delay is used. No. Symbol Parameter Min Typ Max Units 1tDCY Data Clock Period 244 ns 2tDCH Data Clock High Pulse Width (Note 1) 97 3tDCL Data Clock Low Pulse Width (Note 1) 97 4tDCR Rise Time of Clock 25 5tDCF Fall Time of Clock 25 6tICSS Chip Select Setup Time, Input Mode 70 tDCY – 10 7tICSH Chip Select Hold Time, Input Mode 0 tDCH – 20 8tICSL Chip Select Pulse Width, Input Mode 8tDCY 9tICSO Chip Select Off Time, Input Mode (Note 7) 5 µs 10 tIDS Input Data Setup Time 30 ns 11 tIDH Input Data Hold Time 30 12 tOLH SLIC Output Latch Valid 20 1000 13 tOCSS Chip Select Setup Time, Output Mode 70 tDCY – 10 14 tOCSH Chip Select Hold Time, Output Mode 0 tDCH – 20 15 tOCSL Chip Select Pulse Width, Output Mode 8tDCY 16 tOCSO Chip Select Off Time, Output Mode (Note 7) 5 µs 17 tODD Output Data Turn On Delay (Note 5) 50 ns 18 tODH Output Data Hold Time 0 19 tODOF Output Data Turn Off Delay 50 20 tODC Output Data Valid 0 50 No. Symbol Parameter Min Typ Max Units 21 tPCY PCM Clock Period (Note 2) 0.122 7.8125 µs 22 tPCH PCM Clock High Pulse Width 48 3890 ns 23 tPCL PCM Clock Low Pulse Width 48 3890 24 tPCF Fall Time of Clock 15 25 tPCR Rise Time of Clock 15 26 tFSS FS Setup Time 25 tPCY – 50 27 tFSH FS Hold Time 50 28 tTSD Delay to TSC Valid (with Programmable Delay) (Note 3) 5 30 80 150 29 tTSO Delay to TSC Off (with Programmable Delay) (Note 6) 5 30 80 150 30 tDXD PCM Data Output Delay (with Programmable Delay) (Note 4) 3 30 80 150 31 tDXH PCM Data Output Hold Time (with Programmable Delay) (Note 4) 5 30 80 150 32 tDXZ PCM Data Output Delay to HI-Z (with Programmable Delay) (Note 4) 5 30 80 150 33 tDRS PCM Data Input Setup Time 25 34 tDRH PCM Data Input Hold Time 5 |
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