AM79C02AJC datasheet(24/48 Pages) AMD

24 / 48 page

Am79C02/03/031(A) Data Sheet

fractional time slot after the last full time slot in the

frame contains random information and has the TSC

output turned on. For example, if the PCLK frequency

is 1.544 MHz (R = 1) and the transmit clock slot is

greater than 1, the 1-bit fractional time slot after the last

full time slot in the frame contains random information,

and the TSC output remains active during the fractional

time slot. The data is transmitted in bytes, with the most

significant bit first.

The PCM data may be user programmed for output onto

either the DXA or DXB port. Correspondingly, either

TSCA or TSCB is Low during transmission.

The DXA/DXB and TSCA/TSCB outputs can be pro-

grammed to change either on the negative or positive

edge of PCLK. In the first case, an extra delay (PCM

delay) in the timing of the DXA and DXB signals may be

programmed to allow timing compatibility with other de-

vices on the PCM highway.

Receive Signal Processing

In the receive path, the digital signal is expanded, fil-

tered, converted to analog, and passed to the VOUT

pin. The signal processor contains an ALU, RAM, ROM,

and control logic to implement the filter sections. The Z,

R, and GR blocks are user-programmable filter sections

with their coefficients stored in the coefficient RAM,

while AR is an analog amplifier that can be programmed

for a 0 dB or 6.02 dB loss. The filters may be made

transparent when not required in a system.

The low-pass filter band limits the signal. The R filter is

a six tap FIR section operating at a 16 kHz sampling

rate and is part of the frequency response correction

network. The Analog Impedance Scaling Network

(AISN) is a user-programmable gain block providing

feedback from VIN to VOUT to emulate different ZSLIC

impedances from a single external ZSLIC impedance.

The Z filter provides feedback from the transmit signal

path to the receive path and is used to modify the effec-

tive input impedance to the system. The interpolator

increases the sampling rate prior to D/A conversion.

Receive PCM Interface

The receive PCM interface logic controls the reception

of data bytes from the PCM highway, transfers the data

to the A-law/µ-law expansion logic, and then passes the

data to the receive path of the signal processor. The

frame sync (FS) pulse identifies the beginning of a re-

ceive frame, and all channels (time slots) are referenced

to it.

The logic contains user-programmable Receive Time

Slot and Receive Clock Slot registers. The Time Slot

nels (using a PCLK of 8.192 MHz) in each frame. This

feature allows any clock frequency between 128 kHz

and 8.192 MHz (2 to 128 channels) in a system. The

Clock Slot register is 3 bits wide and may be pro-

grammed to offset the time slot assignment by 0 to 7

PCLK periods to eliminate any clock skews in the sys-

tem. An exception occurs when division of the PCLK

frequency by 64 kHz produces a nonzero remainder, R

(R = fPCLK modulo 64 kHz, R > 0) and when the receive

clock slot is greater than R. In that case, the last receive

time slot in the frame is not usable. For example, if the

PCLK frequency is 1.544 MHz (R = 1), the receive clock

slot can be only 0 or 1 if the last time slot is to be used.

The PCM data may be user programmed for input from

either the DRA or DRB port.

Analog Impedance Scaling Network (AISN)

The AISN is incorporated in the DSLAC device to scale

the value of the external ZSLIC impedance. Scaling this

external impedance with the AISN (along with the Z fil-

ter) allows matching of many different line conditions

using a single impedance value. Linecards may be de-

signed for many different specifications without any

hardware changes.

The AISN is a programmable gain that is connected

across the DSLAC device input from VIN to VOUT. The

gain can be varied from –0.9375 to +0.9375 in 31

steps of 0.0625. The AISN gain is given by the follow-

ing equation:

where A, B, C, D, and E = 1 or 0.

The AISN gain is used to alter the input impedance of

the DSLAC device from the SLIC as given by:

where G440 (defined as G24 G42 + G44) is the echo

gain into an open circuit and G44 is the echo gain into

a short circuit.

There are two special cases to the formula for hAISN:

1) value of ABCDE = 00000 specifies a gain of 0 (or

cutoff), and 2) a value of ABCDE = 10000 is a special

case where the AISN circuitry is disabled and the VOUT

pad is connected internally to VIN with a gain of 0 dB.

This allows a digital-to-digital Loopback mode wherein

a digital PCM input signal is completely processed

through the receive section all the way to the VOUT pin.

The signal then is connected internally to VIN where it

is processed through the transmit section and output as

digital PCM data.

Speech Coding

The A/D and D/A conversion follows either the A-law or

the µ-law as they are defined in CCITT Rec. G.711. A-

law or µ-law operation is programmed using MPI Com-

mand 19. Alternate bit inversion is performed as part

of the A-law coding.

AISN

0.0625 A2

() 16

–

[]

44hAISN

–

()

440hAISN

–

()

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