AM79C02AJC datasheet(29/48 Pages) AMD

29 / 48 page

SLAC Products

11. Write Transmit Clock Slot, Receive Clock Slot, and Transmit Clock Edge

(44h)

TCS:

Transmit Clock Slot number 0–7

RCS:

Receive Clock Slot number 0–7

XE=0

Transmit on negative edge of PCLK

XE = 1

Transmit on positive edge of PCLK

RSVD:

Reserved. Always write as 0, but 0 is not guaranteed when read.

Note:

XE = 1 should not be programmed unless the PCM delay is removed (i.e., PCD = 1).

The XE bit is set for both channels when written to either channel. If XE = 1, the

maximum PCM clock rate becomes 4.096 MHz.

12. Read Transmit Clock Slot, Receive Clock Slot, and Transmit Clock Edge

(45h)

RSVD:

Reserved. Always write as 0, but 0 is not guaranteed when read.

13. Write AISN, PCM Delay, and Analog Gains

(50h)

PCM Delay:

PCD = 0*

Delay inserted (SLAC device compatible)

PCD = 1

Delay removed (high speed)

Transmit Analog Gain:

AX = 0*

0 dB gain

AX = 1

6.02 dB gain

Receive Analog Loss:

AR = 0*

0 dB loss

AR = 1

6.02 dB loss

AISN coefficient: A, B, C, D, E

The Analog Impedance Scaling Network (AISN) gain can be varied from –0.9375

to 0.9375 in multiples of 0.0625. The gain coefficient is decoded using the follow-

ing equation:

where hAISN is the gain of the AISN and A, B, C, D, and E = 0 or 1. A value of ABCDE

= 10000 implements a special digital Loopback mode, and a value of ABCDE = 00000

indicates a gain of 0 (cutoff).

* Power-up default value.

Note:

Maximum PCLK frequency with PCM delay inserted (PCD = 0) is: 4.096 MHz.

Command

Input Data

RSVD

RCS

TCS

Command

Output Data

RSVD

RCS

TCS

Command

Input Data

PCD

AISN

0.0625 A

•

() 16

–

[]

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