AM79C02AJC datasheet(23/48 Pages) AMD

23 / 48 page

SLAC Products

Distortion Correction and Equalization

The DSLAC device contains programmable filters in the

receive (R) and transmit (X) directions that may be pro-

grammed for line equalization and to correct any atten-

uation distortion caused by the Z filter.

Transhybrid Balancing

The DSLAC device’s programmable B filter is used to

adjust transhybrid balance. The filter has a single pole

IIR section (BIIR) and an eight tap FIR section (BFIR),

both operating at 16 kHz. The DSLAC device has an

optional Adaptive mode for the B filter, which may be

used to achieve optimum performance. The Echo

Path Gain (EPG) and Error Level Threshold (ELT) reg-

isters contain values that determine the Adaptive

mode performance.

Gain Adjustment

The DSLAC device’s transmit path has two programma-

ble gain blocks. Gain block AX is an analog gain of 0 dB

or 6.02 dB, located immediately before the A/D convert-

er. Gain block GX is a digital gain that is programmable

to any gain from 0 dB to 12 dB with a worst-case step

size of 0.3 dB for gain settings above 10 dB. The filters

provide a net gain in the range of 0 dB to 18 dB.

The DSLAC device receive path has two programmable

loss blocks. Loss block GR is a digital loss that is pro-

grammable from 0 dB to 12 dB with a worst-case step

size of 0.1 dB. Loss block AR is an analog loss of 0 dB

or 6.02 dB, located immediately after the D/A converter.

This provides a net loss in the range of 0 dB to 18 dB.

Transmit Signal Processing

In the transmit path, the analog input signal is A/D con-

verted, filtered, companded (A-law or µ-law), and made

available for output to the PCM highway. The signal pro-

cessor contains an ALU, RAM, ROM, and control logic

to implement the filter sections. The B, X, and GX blocks

are user-programmable digital filter sections with coef-

ficients stored in the coefficient RAM while AX is an

analog amplifier that can be programmed for 0 dB or

6.02 dB gain. The filters may be made transparent when

not required in a system.

The decimator reduces the high input sampling rate to

16 kHz for input to the B, GX, and X filters. The X filter

is a six tap FIR section, which is part of the frequency

response correction network. The B filter operates on

samples from the receive signal path in order to provide

transhybrid balancing in the loop. The high-pass filter

rejects low frequencies such as 50 or 60 Hz and may

be disabled.

Transmit PCM Interface

The transmit PCM interface receives an 8-bit com-

pressed code from the digital A-law/µ-law compressor.

Transmit logic controls the transmission of data onto the

PCM highway through output port selection and time/

clock slot control circuitry.

The frame sync (FS) pulse identifies the beginning of a

transmit frame and all channels (time slots) are refer-

enced to it. The logic contains user programmable

Transmit Time Slot and Transmit Clock Slot registers.

The Time Slot register is 7 bits wide and allows up to

128 8-bit channels (using a PCLK of 8.192 MHz) in each

frame. This feature allows any clock frequency between

128 kHz and 8.192 MHz (2 to 128 channels) in a system.

The Clock Slot register is 3 bits wide and may be pro-

grammed to offset the time slot assignment by 0 to 7

PCLK periods to eliminate any clock skew in the system.

The data is transmitted in bytes with the most significant

bit first.

An exception occurs when division of the PCLK fre-

quency by 64 kHz produces a nonzero remainder, R

(R = fPCLK modulo 64 kHz, R > 0), and when the trans-

mit clock slot is greater than R. In that case, the R-bit

TSA

AISN

TX Cutoff

Digital

Loop-

back

(#13)

TSA Loopback

(also uses

TX Cutoff)

(#21)

ADC

Decimator

& HPF

DAC

LPF

& HPF

Compressor

Expander

LPF

VOUT

VIN

TSA

Inter-

polator

Digital

Inter-

polator

Deci-

mator

PCM

Highway

Cutoff

Analog Loopback

(also uses

RX Cutoff)

(#21)

Figure 8.

DSLAC Block Diagram

09875H-018

* programmable blocks

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