ADPA7008CHIP

Data Sheet

Rev. 0 | Page 6 of 26

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

RFOUT

RFIN

VDET

VREF

24

5

6

7

8

9

10

1

3

ADPA7008CHIP

TOP VIEW

(Not to Scale)

Figure 2. Pin Configuration

Table 8. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

RFIN

RF Signal Input. This pad is ac-coupled and matched to 50 Ω. See Figure 6 for the interface schematic.

2, 10

Amplifier Gate Controls. External bypass capacitors of 4.7 μF, 0.01 μF, and 100 pF are required for these pads.

3, 4, 8, 9

Drain Biases for the Amplifier. External bypass capacitors of 4.7 μF, 0.01 μF, and 100 pF are required for these

pads. See Figure 9 for the interface schematic.

5

VREF

Reference Diode Voltage. Use this pad for temperature compensation of the VDET RF output power

measurements. Used in combination with VDET, this voltage provides temperature compensation to the VDET

RF output power measurements. See Figure 4 for the interface schematic.

6

RFOUT

RF Signal Output. This pad is ac-coupled and matched to 50 Ω. See Figure 8 for the interface schematic.

7

VDET

Detector Diode Used for Measuring the RF Output Power. Detection via this pad requires the application of a

dc bias voltage through an external series resistor. Used in combination with VREF, the difference detector

voltage, VREF − VDET, is a temperature compensated dc voltage proportional to the RF output power. See

Figure 5 for the interface schematic.

Die Bottom

GND

Ground. The die bottom must be connected to RF and dc ground. See Figure 3 for the interface schematic.