ADPA7008CHIP datasheet(16/26 Pages) AD

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ADPA7008CHIP

Data Sheet

Rev. 0 | Page 16 of 26

THEORY OF OPERATION

The architecture of the ADPA7008CHIP, a medium power

amplifier, is shown in Figure 55. The ADPA7008CHIP uses

two cascaded, four-stage amplifiers operating in quadrature

between six 90° hybrids.

The input signal is divided evenly into two, and then each

signal is divided into two again. Each of these new paths are

amplified through four independent gain stages. The amplified

signals are then combined at the output. This balanced amplifier

approach forms an amplifier with a combined gain of 18 dB and

a PSAT value of 31 dBm.

A portion of the RF output signal is directionally coupled to a

diode for detection of the RF output power. When the diode is

dc biased, the diode rectifies the RF power and makes the RF

power available for measurement as a dc voltage at VDET. To

allow temperature compensation of VDET, an identical and

symmetrically located circuit, minus the coupled RF power, is

available via VREF. Taking the difference of VREF − VDET

provides a temperature compensated signal that is proportional

to the RF output (see Figure 55).

The 90° hybrids ensure that the input and output return losses

are greater than 14 dB. See the application circuits shown in

Figure 56 and Figure 57 for further details on biasing the

various blocks.

VDD2 VDD4

RFOUT

VREF

VGG1 VGG2

VDD1 VDD3

RFIN

DIRECTIONAL

COUPLER

VDET

Figure 55. ADPA7008CHIP Architecture

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