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Data Sheet

ADPA7008CHIP

Rev. 0 | Page 17 of 26

APPLICATIONS INFORMATION

The ADPA7008CHIP is a GaAs, pHEMT, MMIC power amplifier.

Capacitive bypassing is required for all VGGx and VDDx pads.

VGG1 is the gate bias pad for the top cascaded amplifiers. VGG2 is

the gate bias pad for the bottom cascaded amplifiers. VDD1 and

VDD3 are the drain bias pads for the top cascaded amplifiers. VDD2

and VDD4 are the drain bias pads for the bottom cascaded

amplifiers.

All measurements for this device were taken using the primary

application circuit (see Figure 56) and were configured as

shown in the assembly diagram (see Figure 65).

The recommended bias sequence during power-up is as

follows:

Connect GND to RF and dc ground.

Set the gate bias voltages, VGG1 and VGG2, to −1.5 V.

Set all the drain bias voltages, VDDx, to 5 V.

Increase the gate bias voltages, VGG1 and VGG2, to achieve

an IDQ of 1500 mA.

Apply the RF signal.

The recommended bias sequence during power-down is as

follows:

Turn off the RF signal.

Decrease the gate bias voltages, VGG1 and VGG2, to −1.5 V to

achieve a IDQ = 0 mA (approximately).

Decrease all the drain bias voltages, VDDx, to 0 V.

Increase the gate bias voltages, VGG1 and VGG2, to 0 V.

The VDD = 5 V and IDQ = 1500 mA bias conditions are

recommended to optimize overall performance. Unless otherwise

noted, the data shown was taken using the recommended bias

conditions. Operation of the ADPA7008CHIP at different bias

conditions may provide performance that differs from what is

shown in Table 1, Table 2, Table 3, and Table 4. Biasing the

ADPA7008CHIP for higher drain current typically results in

higher P1dB and gain at the expense of increased power

consumption (see Table 9).

TYPICAL APPLICATION CIRCUIT

Figure 56 shows the primary application circuit. Figure 57

shows the alternate primary application circuit.

Table 9. Power Selection Table1, 2

IDQ (mA)

Gain (dB)

P1dB (dBm)

Output IP3 (dBm)

PDISS (W) at PSAT

VGGx (V)

1300

18.9

30.0

39.8

7.9

−0.65

1500

19.6

30.4

38.4

8.4

−0.6

1700

20.1

30.7

36.6

8.9

−0.55

1 Data taken at the following nominal bias conditions: VDD = 5 V, TA = 25°C, and frequency = 36 GHz.

2 Adjust VGG1 from −1.5 V to 0 V to achieve the desired drain current.

VGG1

4.7µF

0.01µF

100pF

4.7µF

0.01µF

100pF

VDD1,

VDD2

RFIN

RFOUT

4.7µF

0.01µF

100pF

VDD3,

VDD4

VDET

VREF

100kΩ

+5V

10kΩ

–

VOUT = VREF – VDET

–5V

10kΩ

SUGGESTED CIRCUIT

Figure 56. Primary Application Circuit

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