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LP87702 数据表(PDF) 39 Page - Texas Instruments |
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LP87702 数据表(HTML) 39 Page - Texas Instruments |
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39 / 98 page  The type of output, either push-pull (with V(VANA) level) or open drain, are set with the GPO0_OD and GPO1_PG1_OD bits in the GPO_CONTROL_1 register and the GPO2_OD bit in the GPO_CONTROL_2 register. The logic level of the GPOx pins are is set by the GPO0_OUT and GPO1_OUT bits in the GPO_CONTROL_1 register and the GPO2_OUT bit in the GPO_CONTROL_2 register. The control of the GPOs can be included to start-up and shutdown sequences. The GPO control for a sequence with ENx pin is selected by the GPOx_EN_PIN_CTRL bits. The delays during start-up and shutdown are set by bits in the GPOx_DELAY registers. 7.3.13 Digital Signal Filtering The digital signals have a debounce filtering. The signal or supply is sampled with a clock signal and a counter. This results as an accuracy of one clock period for the debounce window. Table 7-7. Digital Signal Filtering EVENT SIGNAL/SUPPLY RISING EDGE FALLING EDGE LENGTH LENGTH Enable or Disable for BUCKx, BOOST, or GPOx ENx 3 µs(1) 3 µs(1) VANA undervoltage lockout VANA Immediate (VANA voltage rising) Immediate (VANA voltage falling) VANA overvoltage VANA 1 µs (VANA voltage rising) 1 µs (VANA voltage falling) Thermal warning TDIE_WARN_INT 20 µs 20 µs Thermal shutdown TDIE_SD_INT 20 µs 20 µs Current limit, BUCKx 20 µs 20 µs Current limit, BOOST 64 µs 64 µs Overload FB_B0, FB_B1, VOUT_BST 1 ms N/V PGx pin and power-good interrupt (voltage monitoring) PG0, PG1 / FB_B0, FB_B1 6 µs 6 µs PGx pin and power-good interrupt (voltage monitoring) PG0, PG1 / VOUT_BST, VANA, VMON1, VMON2 15 µs 15 µs (1) No glitch filtering; only synchronization. 7.4 Device Functional Modes 7.4.1 Modes of Operation SHUTDOWN: The V(VANA) voltage is below the VANAUVLO threshold level or the NRST signal is low. All switch, reference, control, and bias circuitry of the LP87702 device are turned off. READ OTP: The main supply voltage (V(VANA)) is above the VANAUVLO level and the NRST signal is high. The converters are disabled and the reference and bias circuitry of the LP87702 are enabled. The OTP bits are loaded to the registers. I2C access is not allowed during OTP read. Section 7.3.8 shows how this also applies to the watchdog. STANDBY: The main supply voltage (V(VANA)) is above the VANAUVLO level and the NRST signal is high. All registers can be read or written by the host processor through the system serial interface. Watchdog is active and the WDI input is expected to toggle to avoid watchdog expiration. The converters are disabled and the LP87702's reference, control, and bias circuitry are enabled. The converters can be enabled if needed. ACTIVE: The main supply voltage (V(VANA)) is above the VANAUVLO level and the NRST signal is high. At least one converter is enabled. All registers can be read or written by the host processor through the system's serial interface. Watchdog is active and the WDI input is expected to toggle to avoid watchdog expiration. www.ti.com LP87702 SNVSBU3 – MARCH 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 39 Product Folder Links: LP87702 |
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