LP87702 datasheet(49/98 Pages) TI

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Table 7-16. BUCK1_CTRL_2 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

2-0

BUCK1_SLEW_RATE

R/W

Sets the output voltage slew rate for BUCK1 converter (rising and

falling edges):

0x0 – Reserved

0x1 – Reserved

0x2 – 10 mV/μs

0x3 – 7.5 mV/μs

0x4 – 3.8 mV/μs

0x5 – 1.9 mV/μs

0x6 – 0.94 mV/μs

0x7 – 0.47 mV/μs

(Default from OTP memory)

7.6.1.1.7 BUCK0_VOUT Register (Offset = 6h) [reset = 0h]

BUCK0_VOUT is shown in Figure 7-25 and described in Table 7-17.

Return to Table 7-9.

Figure 7-25. BUCK0_VOUT Register

BUCK0_VSET

R/W-0h

Table 7-17. BUCK0_VOUT Register Field Descriptions

Bit

Field

Type

Reset

Description

7-0

BUCK0_VSET

R/W

Output voltage of BUCK0 converter:

0x00 ... 0x13, Reserved, DO NOT USE

0.7 V – 0.73 V, 10 mV steps

0x14 – 0.7 V

...

0x17 – 0.73 V

0.73 V – 1.4 V, 5 mV steps

0x18 – 0.735 V

...

0x9D – 1.4 V

1.4 V – 3.36 V, 20 mV steps

0x9E – 1.42 V

...

0xFF – 3.36 V

(Default from OTP memory)

7.6.1.1.8 BUCK1_VOUT Register (Offset = 7h) [reset = 0h]

BUCK1_VOUT is shown in Figure 7-26 and described in Table 7-18.

Return to Table 7-9.

Figure 7-26. BUCK1_VOUT Register

BUCK1_VSET

R/W-0h

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LP87702

SNVSBU3 – MARCH 2021

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