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LP87702 数据表(PDF) 42 Page - Texas Instruments

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部件名 LP87702
功能描述  LP87702 Dual Buck Converter and 5-V Boost With Diagnostic Functions
PDF  98 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

LP87702 数据表(HTML) 42 Page - Texas Instruments

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SCL
SDA
tLOW
trCL
tHD;DAT
tHIGH
tfCL
tSU;DAT
tSU;STA
tSU;STO
START
REPEATED
START
STOP
tHD;STA
START
tSP
trDA
tBUF
tfDA
tHD;STA
S
RS
P
S
Figure 7-17. I2C-Compatible Timing
7.5.1.3 Transferring Data
Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first.
Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated
by the master. The master releases the SDA line (HIGH) during the acknowledge clock pulse. The LP87702
pulls down the SDA line during the 9th clock pulse, signifying an acknowledge. The LP87702 generates an
acknowledge after each byte has been received.
There is one exception to the acknowledge after every byte rule. When the master is the receiver, it must
indicate to the transmitter an end of data by not acknowledging (negative acknowledge) the last byte clocked out
of the slave. This negative acknowledge still includes the acknowledge clock pulse (generated by the master),
but the SDA line is not pulled down.
Note
If the V(VANA) voltage is below the VANAUVLO threshold level during I2C communication, the LP87702
device does not drive the SDA line. The ACK signal and data transfer to the master is disabled at that
time.
The bus master sends a chip address after the START condition. This address is seven bits long followed by an
eighth bit which is a data direction bit (READ or WRITE). A 0 indicates a WRITE and a 1 indicates a READ for
the eighth bit. The second byte selects the register to which the data is written. The third byte contains data to
write to the selected register.
START
MSB Chip Address LSB
ACK from slave
ACK from slave
ACK from slave
SCL
SDA
START
id = 0x60
W ACK
address = 0x40
ACK
ACK
address 0x40 data
STOP
W ACK MSB Register Address LSB ACK
MSB
Data LSB
ACK STOP
Figure 7-18. Write Cycle (w = write; SDA = 0), id = Device Address = 60Hex for LP87702
LP87702
SNVSBU3 – MARCH 2021
www.ti.com
42
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Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: LP87702



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