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F28384SPTPQR 数据表(PDF) 4 Page - Texas Instruments |
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F28384SPTPQR 数据表(HTML) 4 Page - Texas Instruments |
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4 / 306 page  3.1 Functional Block Diagram The Functional Block Diagram shows the CPU system and associated peripherals. 4x ADC (16-bit / 12-bit) C28 CPU2 FPU64 FPU32 TMU VCRC CPU2.CLA1 Arm Cortex-M4 S0-S3 RAM (64KB) E0 RAM (16KB) Boot ROM C0-C1 RAM (16KB) Flash (512KB) CPU2.DMA CPU1.DMA AES CPU Timers GCRC NVIC NMI WD Windowed WD CM µDMA C28 CPU1 FPU64 FPU32 TMU VCRC BGCRC CPU Timers DCC ePIE ERAD NMI WD Windowed WD GS0-GS15 RAM (128KB) 8x FSIRX 2x FSITX 2x McBSP 1x PMBUS 4x SPI 2x I2C 4x SCI 7x eCAP (2 Hi-Res) 32x ePWM Channels (16 Hi-Res) 3x eQEP 8x SD Filters 8x CMPSS 3x DAC PF1 PF9 PF2 PF5 PF6 EMIF1 EMIF2 Result PF3 169x GPIO INPUT XBAR PF4 OUTPUT XBAR Secure ROM Boot ROM D0-D1 RAM (8KB) M0-M1 RAM (4KB) CLA ROM 2x CAN 1x USB 1x CM-I2C 1x CM-UART 1x SSI 1x CAN-FD 1x Ethernet 1x EtherCAT (2 Ports) Data Secure ROM CPU - CLA MSGRAM DMA - CLA MSGRAM MSGRAM0 CPU1 - CPU2 IPC MSGRAM1 ePWM XBAR BGCRC CPU Timers ePIE ERAD NMI WD Windowed WD CM Bus Matrix CPU1 CPU1.CLA CPU1.DMA CPU2 CPU2.CLA CPU2.DMA CM M4 SYS CM M4 CODE CM µDMA Secure Memories shown in Red MUX MUX MUX DMA Ethernet DMA CM Bus Matrix CPU1.CLA1 LS0-LS7 RAM (32KB) Secure ROM Boot ROM D0-D1 RAM (8KB) M0-M1 RAM (4KB) CPU - CLA MSGRAM DMA - CLA MSGRAM Flash (512KB) Flash (512KB) LS0-LS7 RAM (32KB) BGCRC CLA ROM BGCRC CPU1 - CM IPC MSGRAM0 MSGRAM1 Connectivity Manager (CM) CPU2 - CM IPC MSGRAM0 MSGRAM1 P 10 F 8x CLB CLB XBAR CLB INPUT XBAR CLB OUTPUT XBAR MUX Figure 3-1. Functional Block Diagram TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1 TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1 SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021 www.ti.com 4 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TMS320F28388D TMS320F28386D TMS320F28386D-Q1 TMS320F28384D TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S TMS320F28384S-Q1 |
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