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F28384SPTPQR 数据表(PDF) 72 Page - Texas Instruments |
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F28384SPTPQR 数据表(HTML) 72 Page - Texas Instruments |
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72 / 306 page  Table 6-5. Test, JTAG, and Reset (continued) SIGNAL NAME DESCRIPTION PIN TYPE GPIO 337 BGA 176 Pin XRSn Device Reset (in) and Watchdog Reset (out). During a power-on condition, this pin is driven low by the device. An external circuit may also drive this pin to assert a device reset. This pin is also driven low by the MCU when a watchdog reset occurs. During watchdog reset, the XRSn pin is driven low for the watchdog reset duration of 512 OSCCLK cycles. A resistor between 2.2 kΩ and 10 kΩ should be placed between XRSn and VDDIO. If a capacitor is placed between XRSn and VSS for noise filtering, it should be 100 nF or smaller. These values will allow the watchdog to properly drive the XRSn pin to VOL within 512 OSCCLK cycles when the watchdog reset is asserted. The output buffer of this pin is an open-drain with an internal pullup. If this pin is driven by an external device, it should be done using an open-drain device. If this pin is driven by an external device, it should be done using an open-drain device. I/OD F19 124 6.4 Pins With Internal Pullup and Pulldown Some pins on the device have internal pullups or pulldowns. Table 6-6 lists the pull direction and when it is active. The pullups on GPIO pins are disabled by default and can be enabled through software. In order to avoid any floating unbonded inputs, the Boot ROM will enable internal pullups on GPIO pins that are not bonded out in a particular package. Other pins noted in Table 6-6 with pullups and pulldowns are always on and cannot be disabled. Table 6-6. Pins With Internal Pullup and Pulldown PIN RESET (XRSn = 0) DEVICE BOOT APPLICATION SOFTWARE GPIOx Pullup disabled Pullup disabled(1) Pullup enable is application- defined TRSTn Pulldown active TCK Pullup active TMS Pullup active TDI Pullup active XRSn Pullup active ERRORSTS Pulldown active DACOUTx Pulldown active Other pins No pullup or pulldown present (1) Pins not bonded out in a given package will have the internal pullups enabled by the Boot ROM. 6.5 Pin Multiplexing GPIO muxed pins are listed in the GPIO Muxed Pins table in Section 6.5.1. TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1 TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1 SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021 www.ti.com 72 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TMS320F28388D TMS320F28386D TMS320F28386D-Q1 TMS320F28384D TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S TMS320F28384S-Q1 |
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