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F28384SPTPQR 数据表(PDF) 104 Page - Texas Instruments |
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F28384SPTPQR 数据表(HTML) 104 Page - Texas Instruments |
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104 / 306 page  7.10.3.2 Clock Frequencies, Requirements, and Characteristics This section provides the frequencies and timing requirements of the input clocks, PLL lock times, frequencies of the internal clocks, and the frequency and switching characteristics of the output clock. 7.10.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times Section 7.10.3.2.1.1 lists the frequency requirements for the input clocks. Section 7.10.3.2.1.2 lists the XTAL oscillator characteristics. Section 7.10.3.2.1.3 and Section 7.10.3.2.1.4 list the timing requirements for the input clocks. Section 7.10.3.2.1.5 lists the PLL lock times for SYSPLL and AUXPLL. 7.10.3.2.1.1 Input Clock Frequency MIN MAX UNIT f(XTAL) Frequency, X1/X2, from external crystal or resonator 10 20 MHz f(X1) Frequency, X1, from external oscillator 10 25 MHz f(AUXI) Frequency, AUXCLKIN, from external oscillator 10 60 MHz 7.10.3.2.1.2 XTAL Oscillator Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER MIN TYP MAX UNIT X1 VIL Valid low-level input voltage –0.3 0.3 * VDDIO V X1 VIH Valid high-level input voltage 0.7 * VDDIO VDDIO + 0.3 V 7.10.3.2.1.3 X1 Timing Requirements MIN MAX UNIT tf(X1) Fall time, X1 6 ns tr(X1) Rise time, X1 6 ns tw(X1L) Pulse duration, X1 low as a percentage of tc(X1) 45% 55% tw(X1H) Pulse duration, X1 high as a percentage of tc(X1) 45% 55% 7.10.3.2.1.4 AUXCLKIN Timing Requirements MIN MAX UNIT tf(AUXI) Fall time, AUXCLKIN 6 ns tr(AUXI) Rise time, AUXCLKIN 6 ns tw(AUXL) Pulse duration, AUXCLKIN low as a percentage of tc(XCI) 45% 55% tw(AUXH) Pulse duration, AUXCLKIN high as a percentage of tc(XCI) 45% 55% 7.10.3.2.1.5 APLL Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER MIN TYP MAX UNIT PLL Lock Time SYSPLL / AUXPLL Lock time(1) 5µs + (1024 * (REFDIV + 1) * tc(OSCCLK)) µs (1) The PLL lock time here defines the typical time that takes for the PLL to lock once PLL is enabled (SYSPLLCTL1[PLLENA]=1 or AUXPLLCTL1[PLLENA]=1). Additional time to verify the PLL clock using Dual Clock Comparator (DCC) is not accounted here. TI recommends using the latest example software from C2000Ware for initializing the PLLs. For the system PLL, see InitSysPll() or SysCtl_setClock(). For the auxiliary PLL, see InitAuxPll() or SysCtl_setAuxClock(). TMS320F28388D, TMS320F28386D, TMS320F28386D-Q1 TMS320F28384D, TMS320F28384D-Q1, TMS320F28388S TMS320F28386S, TMS320F28386S-Q1, TMS320F28384S, TMS320F28384S-Q1 SPRSP14D – MAY 2019 – REVISED FEBRUARY 2021 www.ti.com 104 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TMS320F28388D TMS320F28386D TMS320F28386D-Q1 TMS320F28384D TMS320F28384D-Q1 TMS320F28388S TMS320F28386S TMS320F28386S-Q1 TMS320F28384S TMS320F28384S-Q1 |
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