ADRF6612ACPZ-R7 datasheet(32/57 Pages) AD

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ADRF6612

Data Sheet

Rev. A | Page 32 of 57

1 TO 8191

(REG 0x21[11:0])

N = INT +

FRAC

MOD

(REG 0x02, REG 0x03,

REG 0x04)

PFD

MIXER 1 LO

MIXER 2 LO

EXTERNAL

LO INPUT

CHARGE

PUMP

2×

PRESCALER

CPOUT

C18

C20

C22

R10

C23

VCOVTUNE

LOOP FILTER

GNDCP

REFIN

LO DIVIDER

(1, 2, 4, 8, 16, 32)

(REG 0x22[5:3])

Figure 93. LO Generation Block Diagram

Loop Filters

Defining a loop filter for the ADRF6612 depends on several

dynamics, these being the PLL REFIN and PFD frequency and

desired PFD and fractional spur levels. Higher reference and

PFD frequencies spread the PFD spurs over a wider bandwidth

(wider separation between spurs), but also lead to higher levels

of spurs coupling through the reference divider chain. Lower

reference and PFD frequencies lower the spacing between PFD

spurs, but the spur levels can be significantly improved by using

lower frequencies. At lower PFD frequencies, it may also be

possible to achieve the desired synthesizer frequency step size

using the integer divider mode, therefore eliminating the risk of

fractional spurs. Table 17 shows the recommended loop filter

components and dynamic loop settings when using integer

mode and PFD frequencies at less than 10 MHz.

Table 17. Integer Mode Loop Filter Components and PLL

Dynamic Settings

Loop Filter Components

PLL Dynamic Settings

C18

1500 pF

910 Ω

C20

33 nF

1.8 kΩ

C22

560 pF

R10

20 kΩ

C23

39 pF

CSCALE

8000 µA

Bleed Current

0 µA

ABDLY

0.9 nS

If a smaller frequency step size is desired, the ADRF6612 can be

used in fractional mode. The 16-bit FRAC_DIV and MOD_DIV

values available in the ADRF6612 mean that small step sizes can

be achieved with high PFD frequencies. PFD spurs may be

higher in amplitude, but are spaced further apart. Fractional

spurs may be present as well.

Table 18. Fractional Mode Loop Filter Components and PLL

Dynamic Settings

Loop Filter Components

PLL Dynamic Settings

C18

1000 pF

700 Ω

C20

33 nF

1.8 kΩ

C22

560 pF

R10

20 kΩ

C23

39 pF

CSCALE

500 µA

Bleed Current

93.75 µA

ABDLY

0 nS

VCOs and Dividers

The ADRF6612 has four internal VCOs. Considering the range

of these VCOs, the fixed 2× prescaler after the VCO, and the

LO_DIV (1, 2, 4, 8, 16, and 32) range, the total LO range allows

RF generation of 200 MHz to 2700 MHz.

Table 19. VCO Range

VCO_SEL (Register 0x22, Bits[2:0])1

Frequency Range (GHz)1

000

VCO_0 = 4.6 to 5.7

001

VCO_1 =4.02 to 4.6

010

VCO_2 =3.5 to 4.02

011

VCO_3 =2.85 to 3.5

For VCO_0, VCO_1, VCO_2, and VCO_3, set VTUNE_DAC_SLOPE (Register 0x49,

Bits[13:9]) = 11 (decimal), VTUNE_DAC_OFFSET (Register 0x49, Bits[8:0]) =

184 (decimal), VCO_LDO_R2 (Register 0x22, Bits[11:8]) = 0 (decimal), and

VCO_LDO_R4 (Register 0x22, Bits[15:12]) = 5 (decimal).

The N-divider divides down the differential VCO signal to the PFD

frequency. The N-divider can be configured for fractional mode or

integer mode by addressing the DIV_MODE bit (Register 0x02,

Bit 15). The default configuration is set for fractional mode.

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