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ADRF6612ACPZ-R7 数据表(PDF) 2 Page - Analog Devices

部件名 ADRF6612ACPZ-R7
功能描述  700 MHz to 3000 MHz Dual Passive Receive Mixer with Integrated PLL and VCO
PDF  57 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADRF6612ACPZ-R7 数据表(HTML) 2 Page - Analog Devices

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ADRF6612
Data Sheet
Rev. A | Page 2 of 57
TABLE OF CONTENTS
Features .............................................................................................. 1
 
Applications....................................................................................... 1
 
Functional Block Diagram .............................................................. 1
 
General Description ......................................................................... 1
 
Revision History ............................................................................... 2
 
Specifications..................................................................................... 3
 
RF Specifications .......................................................................... 3
 
Synthesizer/PLL Specifications................................................... 4
 
VCO Specifications, Open-Loop................................................ 7
 
Logic Input and Power Specifications ....................................... 8
 
Digital Logic Specifications......................................................... 9
 
Absolute Maximum Ratings.......................................................... 10
 
Thermal Resistance .................................................................... 10
 
ESD Caution................................................................................ 10
 
Pin Configuration and Function Descriptions........................... 11
 
Typical Performance Characteristics ........................................... 13
 
Mixer, High Performance Mode............................................... 13
 
Mixer, High Efficiency Mode.................................................... 22
 
Synthesizer................................................................................... 23
 
Spurious Performance ............................................................... 29
 
Circuit Description......................................................................... 31
 
RF Subsystem.............................................................................. 31
 
External LO Generation ............................................................ 31
 
Internal LO Generation ............................................................. 31
 
Applications Information .............................................................. 35
 
Basic Connections Pin Description ............................................. 36
 
Mixer Optimization ....................................................................... 37
 
RF Input Balun Insertion Loss Optimization......................... 37
 
IIP3 Optimization ...................................................................... 37
 
VGS Programming..................................................................... 38
 
Low-Pass Filter Programming.................................................. 38
 
Register Summary .......................................................................... 40
 
Register Details ............................................................................... 41
 
Evaluation Board ............................................................................ 52
 
Outline Dimensions ....................................................................... 57
 
Ordering Guide .......................................................................... 57
 
REVISION HISTORY
5/2016—Rev. 0 to Rev. A
Changes to Table 19........................................................................ 32
Changes to Address: 0x22, Reset: 0x000A, Name: VCO_CTRL1
Section and Table 34....................................................................... 45
Updated Outline Dimensions ....................................................... 57
Changes to Ordering Guide .......................................................... 57
12/2014—Revision 0: Initial Version



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