ADRF6612ACPZ-R7 datasheet(33/57 Pages) AD

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Data Sheet

ADRF6612

Rev. A | Page 33 of 57

The following equations can be used to determine the N value and

the PLL frequency:

VCO

PFD

MOD

FRAC

INT

LO_DIVIDER

PFD

where:

fPFD is the phase frequency detector frequency.

fVCO is the voltage controlled oscillator frequency.

N is the fractional divide ratio.

INT is the integer divide ratio programmed in Register 0x02.

FRAC is the fractional divide ratio programmed in Register 0x03.

MOD is the modulus divide ratio programmed in Register 0x04.

fLO is the LO frequency going to the mixer core when the loop is

locked.

LO_DIVIDER is the final divider block that divides the VCO

frequency down by 1, 2, 4, or 8 before it reaches the mixer

(see Table 20). This control is located in the LO_DIV bits

(Register 0x22, Bits[5:3]).

Table 20. LO Divider

LO_DIV (Register 0x22, Bits[5:3])

LO_DIVIDER

The lock detect signal is available as one of the selectable outputs

through the MUXOUT pin; a logic high indicates that the loop is

locked. The MUXOUT pin is controlled by the REF_MUX_SEL

bits (Register 0x21, Bits[14:13]); the PLL lock detect signal is the

default configuration.

To ensure that the PLL locks to the desired frequency, follow the

proper write sequence of the PLL registers. The PLL registers must

be configured accordingly to achieve the desired frequency, and the

last writes must be to Register 0x02 (INT_DIV in Table 25),

(MOD_DIV in Table 25). When one of these registers is

programmed, an internal VCO calibration is initiated, which is

the last step in locking the PLL.

The time it takes to lock the PLL after the last register is written

can be broken down into two parts: VCO band calibration and

loop settling.

After the last register is written, the PLL automatically performs

a VCO band calibration to choose the correct VCO band. This

calibration takes approximately 5120 PFD cycles. For a 40 MHz

fPFD, this corresponds to 128 µs. After calibration is complete, the

feedback action of the PLL causes the VCO to eventually lock to

the correct frequency. The speed with which this locking occurs

depends on the nonlinear cycle-slipping behavior, as well as the

small-signal settling of the loop. For an accurate estimation of

the lock time, download the ADIsimPLL™ tool, which correctly

captures these effects. In general, higher bandwidth loops tend

to lock faster than lower bandwidth loops.

Additional LO Controls

To access the LO signal going to the mixer core through the

LOOUT+ and LOOUT− pins (Pin 13 and Pin 14), enable the

LO_DRV_EN bit in Register 0x01, Bit 7. This setting offers direct

monitoring of the LO signal to the mixer for debug purposes; or the

LO signal can be used to daisy-chain many devices synchronously.

One ADRF6612 can serve as the master where the LO signal is

sourced, and the subsequent slave devices share the same LO signal

from the master. This flexibility substantially eases the LO

requirements of a system with multiple LOs.

The LO output drive level is controlled by the LO_DRV_LVL bits

(Register 0x22, Bits[7:6]). Table 21 shows the available drive levels.

Table 21. LO Drive Levels

LO_DRV_LVL (Register 0x22, Bits[7:6])

Amplitude (dBm)

−4

0.5

4.5

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