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ADRF6612ACPZ-R7 数据表(PDF) 1 Page - Analog Devices |
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ADRF6612ACPZ-R7 数据表(HTML) 1 Page - Analog Devices |
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1 / 57 page ![]() 700 MHz to 3000 MHz Dual Passive Receive Mixer with Integrated PLL and VCO Data Sheet ADRF6612 Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2014–2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com FEATURES RF frequency: 700 MHz to 3000 MHz, continuous LO input frequency: 200 MHz to 2700 MHz, high-side or low- side injection IF range: 40 MHz to 500 MHz Power conversion gain of 9.0 dB Single sideband (SSB) noise figure of 11.3 dB Input IP3 of 30 dBm Input P1dB of 10.6 dBm Typical LO input drive of 0 dBm Single-ended, 50 Ω RF port Single-ended or balanced LO input port Serial port interface (SPI) control on all functions Exposed pad, 7 mm × 7 mm, 48-lead LFCSP APPLICATIONS Multiband/multistandard cellular base station diversity receivers Wideband radio link diversity downconverters Multimode cellular extenders and picocells FUNCTIONAL BLOCK DIAGRAM GND SPI CONTROL ÷1 TO 32 PLL REF BUFFER PFD/CP FRACTIONAL DIVIDER PLL 3.3V LDO VCO LDO SPI 2.5V LDO DIV 3.3V LDO VCO VCO VCO VCC10 GND GND VCC1 EXTVCOIN+ EXTVCOIN– DECL1 DECL2 DECL3 DECL4 DECL5 VCC9 VCC8 RFBCT1 RFIN1 VCC7 LDO2 RFIN2 RFBCT2 VCC6 VCC5 VCC4 42 43 47 37 40 38 39 41 48 44 45 46 2 1 3 6 34 33 36 35 31 30 26 25 29 28 27 32 7 9 8 5 4 10 11 12 14 15 16 17 18 19 22 23 20 21 24 13 ADRF6612 Figure 1. GENERAL DESCRIPTION The ADRF6612 is a dual radio frequency (RF) mixer and intermediate frequency (IF) amplifier with an integrated phase- locked loop (PLL) and voltage controlled oscillators (VCOs). The ADRF6612 uses revolutionary broadband square wave limiting local oscillator (LO) amplifiers to achieve an unprecedented RF bandwidth of 700 MHz to 3000 MHz. Unlike narrow-band sine wave LO amplifier solutions, the LO can be applied above or below the RF input over an extremely wide bandwidth. Energy storage elements are not utilized in the LO amplifier, thus dc current consumption also decreases with decreasing LO frequency. The ADRF6612 utilizes highly linear, doubly balanced passive mixer cores with integrated RF and LO balancing circuits to allow single-ended operation. Integrated RF baluns allow optimal performance over the 700 MHz to 3000 MHz RF input frequency. The balanced passive mixer arrangement provides outstanding LO to RF and LO to IF leakages, excellent RF to IF isolation, and excellent intermodulation performance over the full RF bandwidth. The balanced mixer cores provide extremely high input linearity, allowing the device to be used in demanding wideband applications where in band blocking signals may otherwise result in the degradation of dynamic range. Noise performance under blocking is comparable to narrow-band passive mixer designs. High linearity IF buffer amplifiers follow the passive mixer cores, yielding typical power conversion gains of 9 dB, and can be matched to a wide range of output impedances. The PLL architecture supports both integer-N and fractional-N operation and can generate the entire LO frequency range of 200 MHz to 2700 MHz using an external reference input frequency anywhere in the range of 12 MHz to 320 MHz. An external loop filter provides flexibility in trading off phase noise vs. acquisition time. To reduce fractional spurs in fractional-N mode, a sigma-delta (Σ-Δ) modulator controls the post-VCO programmable divider. The VCO consists of multiple VCO cores. All features of the ADRF6612 are controlled via a 3-wire SPI resulting in optimum performance and minimum external components. The ADRF6612 is fabricated using a BiCMOS, high performance IC process. The device is available in a 7 mm × 7 mm, 48-lead LFCSP package and operates over a −40°C to +85°C temperature range. An evaluation board is available. |
类似零件编号 - ADRF6612ACPZ-R7 |
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类似说明 - ADRF6612ACPZ-R7 |
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