ADRF6612ACPZ-R7 datasheet(9/57 Pages) AD

部件名	ADRF6612ACPZ-R7

功能描述	700 MHz to 3000 MHz Dual Passive Receive Mixer with Integrated PLL and VCO

PDF	57 Pages

Scroll/Zoom	100%

制造商	AD [Analog Devices]

网页	http://www.analog.com

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9 / 57 page

Data Sheet

ADRF6612

Rev. A | Page 9 of 57

DIGITAL LOGIC SPECIFICATIONS

Table 7.

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

Units

Input Voltage High

VIH

1.4

Input Voltage Low

VIL

0.70

Output Voltage High

VOH

IOH = −100 µA

2.3

Output Voltage Low

VOL

IOL = 100 µA

0.2

Serial Clock Period

tCLK

Setup Time Between Data and Rising Edge of SCLK

tDS

Hold Time Between Data and Rising Edge of SCLK

tDH

Setup Time Between Falling Edge of CS and SCLK

Hold Time Between Rising Edge of CS and SCLK

Minimum Period for SCLK to Be in a Logic High State

tHIGH

Minimum Period for SCLK to Be in a Logic Low State

tLOW

Maximum Delay Between Falling Edge of SCLK and

Output Data Valid for a Read Operation

tACCESS

231

Maximum Delay Between CS Deactivation and SDIO

Bus Return to High Impedance

tDS

tDH

tHIGH

tLOW

tCLK

DON'T CARE

D15

D14

D13

DON'T CARE

SCLK

SDIO

R/W

tACCESS

Figure 2. Setup and Hold Timing Measurements

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