ADRF6614ACPZ-R7 datasheet(34/61 Pages) AD

34 / 61 page

ADRF6614

Data Sheet

Rev. 0 | Page 34 of 61

THEORY OF OPERATION

The ADRF6614 consists of two primary components: the RF

subsystem and the LO subsystem. The combination of design,

process, and packaging technology allows the functions of these

subsystems to be integrated into a single die, using mature

packaging and interconnection technologies to provide a high

performance device with excellent electrical, mechanical, and

thermal properties. The wideband frequency response and flexible

frequency programming simplifies the receiver design, saves

on-board space, and minimizes the need for external components.

The RF subsystem consists of an integrated, tunable, low loss RF

balun, a double balanced, passive MOSFET mixer, a tunable sum

termination network, and an IF amplifier.

The LO subsystem consists of a multistage, limiting LO amplifier.

The purpose of the LO subsystem is to provide a large, fixed ampli-

tude, balanced signal to drive the mixer independent of the level of

the LO input. A schematic of the device is shown in Figure 110.

RF SUBSYSTEM

The single-ended, 50 Ω RF input is internally transformed to a

balanced signal using a tunable, low loss, unbalanced to balanced

(balun) transformer. This transformer is made possible by an

extremely low loss metal stack, which provides both excellent

balance and dc isolation for the RF port. Although the port can

be dc connected, it is recommended to use a blocking capacitor

to avoid running excessive dc current through the device. The RF

balun can easily support an RF input frequency range of 700 MHz

to 3000 MHz. This balun is tuned over the frequency range by a SPI

controlled switched capacitor network at the output of the RF balun.

The resulting balanced RF signal is applied to a passive mixer that

commutates the RF input in accordance with the output of the LO

subsystem. The passive mixer is a balanced, low loss switch that adds

minimum noise to the frequency translation. The only noise con-

tribution from the mixer is due to the resistive loss of the switches,

which is in the order of a few ohms.

The IF amplifier is a balanced feedback design that simultaneously

provides the gain, noise figure, and input impedance required to

achieve the overall performance. The balanced open-collector

output of the IF amplifier, with an impedance modified by the

feedback within the amplifier, permits the output to be connected

directly to a high impedance filter, a differential amplifier, or an

analog-to-digital converter (ADC) input while providing optimum

second-order intermodulation suppression. The differential output

impedance of the IF amplifier is approximately 200 Ω. If operation

in a 50 Ω system is desired, the output can be transformed to 50 Ω

by using a 4:1 transformer or an LC impedance matching network.

EXTERNAL LO GENERATION

The ADRF6614 LO can be generated by an externally applied

source or by using the internal PLL synthesizer. To select the

external LO mode, write 011 to Register 0x22, Bits[2:0] and apply

the differential LO signal to Pin 4 (EXTVCOIN+) and Pin 5

(EXTVCOIN−).

Internal dividers allow the externally applied LO signal to be

divided before this signal arrives at the mixer LO input. The

divider value is set by Register 0x22, Bits[5:3] and has possible

values of 1, 2, 4, and 8. With the divider set to 1, the externally

applied LO input frequency range is 250 MHz to 2850 MHz.

When using a divider value of other than 1, the maximum

externally applied LO frequency is 5700 MHz.

The external LO input pins present a broadband differential 50 Ω

input impedance. The EXTVCOIN+ and EXTVCOIN− input

pins must be ac-coupled. When not in use, EXTVCOIN+ and

EXTVCOIN− can be left unconnected.

INTERNAL LO GENERATION

Reference Input Circuitry

The ADRF6614 includes an on-chip PLL for LO synthesis. The

PLL, shown in Figure 109, consists of a reference input and input

dividers, a PFD, a charge pump, VCOs, and a programmable

fractional/integer divider with a 2× prescaler.

The reference path takes in a reference clock and divides it by a

factor of 1 to 8191 before passing it to the PFD. The PFD compares

this signal to the divided down signal from the VCO. Depending

on the PFD polarity selected, the PFD sends an up or down signal

to the charge pump if the VCO signal is slow or fast compared to

the reference frequency. The charge pump sends a current pulse

to the off-chip loop filter to increase or decrease the tuning

voltage (VCOVTUNE).

1 TO 8191

(REG 0x21[11:0])

N = INT +

FRAC

MOD

(REG 0x02, REG 0x03,

REG 0x04)

PFD

MIXER 1 LO

MIXER 2 LO

EXTERNAL

LO INPUT

CHARGE

PUMP

2×

PRESCALER

CPOUT

C18

C20

C22

R10

C23

VCOVTUNE

LOOP FILTER

GNDCP

REFIN

LO DIVIDER

(1, 2, 4, 8, 16, 32)

(REG 0x22[5:3])

Figure 109. LO Generation Block Diagram

ADRF6614ACPZ-R7 数据表(PDF) 34 Page - Analog Devices

ADRF6614ACPZ-R7 数据表(HTML) 34 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61

数据表下载