ADRF6614ACPZ-R7 datasheet(35/61 Pages) AD

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Data Sheet

ADRF6614

Rev. 0 | Page 35 of 61

In-band (within the band of the loop filter) phase noise perfor-

mance is typically limited by the reference source. Due to the

inherent phase noise reduction when performing frequency

division, improved in-band phase noise performance can be

achieved with higher reference divide values. However, the

divide chain adds its own small amount of phase noise; thus,

there is a limit on how much improvement can be gained by

increasing the divider value.

Loop Filters

Defining a loop filter for the ADRF6614 depends on several

dynamic: the PLL REFIN and PFD frequency and desired PFD

and fractional spur levels. Higher reference and PFD frequencies

spread the PFD spurs over a wider bandwidth (wider separation

between spurs), but also lead to higher levels of spurs coupling

through the reference divider chain. Lower reference and PFD

frequencies lower the spacing between PFD spurs, but the spur

levels can be significantly improved by using lower frequencies.

At lower PFD frequencies, it may also be possible to achieve the

desired synthesizer frequency step size using the integer divider

mode, therefore eliminating the risk of fractional spurs. Table 17

shows the recommended loop filter components and dynamic

loop settings when using integer mode and PFD frequencies at

less than 10 MHz.

Table 17. Integer Mode Loop Filter Components and PLL

Dynamic Settings

Loop Filter Components

PLL Dynamic Settings

C18

1500 pF

910 Ω

C20

33 nF

1.8 kΩ

C22

560 pF

R10

20 kΩ

C23

39 pF

CSCALE

8000 µA

Bleed Current

0 µA

ABLDLY

0.9 ns

If a smaller frequency step size is desired, the ADRF6614 can be

used in fractional mode. The 16-bit FRAC_DIV and MOD_DIV

values available in the ADRF6614 mean that small step sizes

can be achieved with high PFD frequencies. PFD spurs may be

higher in amplitude, but are spaced further apart. Fractional

spurs may be present as well.

Table 18. Fractional Mode Loop Filter Components and PLL

Dynamic Settings

Loop Filter Components

PLL Dynamic Settings

C18

1000 pF

700 Ω

C20

33 nF

1.8 kΩ

C22

560 pF

R10

20 kΩ

C23

39 pF

CSCALE

500 µA

Bleed Current

93.75 µA

ABLDLY

0 ns

For GSM mode of operation at the PFD rate of 1.536 MHz, the

recommended loop filter components and dynamic loop

settings are shown in Table 19.

Table 19. GSM Mode Loop Filter Components and PLL

Dynamic Settings

Loop Filter Components

PLL Dynamic Settings

C18

2200 pF

1.2 kΩ

C20

47 nF

1 kΩ

C22

1200 pF

R10

6.2 kΩ

C23

330 pF

CSCALE

8 mA

Bleed Current

0 µA

ABLDLY

0.9 ns

VCOs and Dividers

The ADRF6614 has six internal VCOs. Considering the range of

these VCOs, the fixed 2× prescaler after the VCO, and the LO_DIV

(1, 2, 4, 8, 16, and 32) range, the total LO range allows an RF

generation of 200 MHz to 2700 MHz.

Table 20. VCO Range

VCO_SEL (Register 0x22, Bits[2:0])

Frequency Range (GHz)

000

4.6 to 5.7

001

4.02 to 4.6

010

3.5 to 4.02

011

2.85 to 3.5

100

3.050 to 3.094

101

3.336 to 3.416

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