LPS27HHTW datasheet(53/55 Pages) STMICROELECTRONICS

53 / 55 page

List of figures

Figure 1.

Device architecture block diagram....................................................... 2

Figure 2.

Digital logic ...................................................................... 2

Figure 3.

Pin connections (bottom view) ......................................................... 3

Figure 4.

SPI slave timing diagram ............................................................. 6

Figure 5.

I²C slave timing diagram ............................................................. 7

Figure 6.

LPS27HHTW internal structure ........................................................ 10

Figure 7.

Pressure readings................................................................. 11

Figure 8.

Temperature readings .............................................................. 11

Figure 9.

Bypass mode .................................................................... 13

Figure 10.

FIFO mode ..................................................................... 14

Figure 11.

Continuous (Dynamic-Stream) mode .................................................... 15

Figure 12.

Bypass-to-FIFO mode .............................................................. 16

Figure 13.

Bypass-to-Continuous (Dynamic-Stream) mode ............................................ 17

Figure 14.

Continuous (Dynamic-Stream)-to-FIFO mode .............................................. 18

Figure 15.

LPS27HHTW electrical connections (top view) ............................................. 19

Figure 16.

LPS27HHTW power-off sequence...................................................... 20

Figure 17.

Read and write protocol ............................................................. 23

Figure 18.

SPI read protocol ................................................................. 24

Figure 19.

Multiple byte SPI read protocol (2-byte example)............................................ 24

Figure 20.

SPI write protocol ................................................................. 25

Figure 21.

Multiple byte SPI write protocol (2-byte example) ........................................... 25

Figure 22.

SPI read protocol in 3-wire mode ...................................................... 26

Figure 23.

I²C and MIPI I3CSM both active (INT_DRDY pin not connected) ................................. 29

Figure 24.

Only MIPI I3CSM active (INT_DRDY pin connected to Vdd_IO) .................................. 30

Figure 25.

“Threshold-based” interrupt event ...................................................... 34

Figure 26.

Interrupt events on INT_DRDY pin ..................................................... 39

Figure 27.

CCLGA - 10L (2.7 x 2.7 x 1.7 typ. mm) package outline and mechanical data ........................ 46

Figure 28.

Carrier tape information for CCLGA-10L package ........................................... 47

Figure 29.

Package orientation in carrier tape ..................................................... 47

Figure 30.

Reel information for carrier tape of CCLGA-10L package ...................................... 48

LPS27HHTW

List of figures

DS13489 - Rev 1

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